AMBA IP
AMBA IP cores and subsystems: AXI, AHB and APB
Silvaco’s AMBA IP gives your SoC team all three buses: AXI, AHB and APB controllers and peripherals, the fabric and bridges between them, and five pre-integrated subsystems, as synthesizable soft IP for MCUs up to multi-core SoCs.
Cores for each bus, or a subsystem that's already wired
Pick individual cores and build your own interconnect. Or start from a subsystem where the fabric and bridges are
joined up before you add a block of your own.
AXI IP
AXI4 and AXI4-Lite controllers for the high-bandwidth end of your interconnect. A QSPI controller with XIP and DMA, an AXI to SPI slave bridge, a 5-master SRAM controller that reaches 64-bit SRAM in zero or one cycle, and an external memory controller that drives up to four devices.
AHB IP
The system-bus set, on AHB and AHB-Lite. You get an octal and quad SPI controller, a round-robin arbiter for up to four masters, DES and triple DES, AES with DMA, single- and quad-channel DMA, and SRAM, parallel flash, external bus and TFT LCD controllers.
APB IP
For the low-power, low-bandwidth corner of your SoC: APB 2.0 GPIO, a real-time clock, an interrupt controller, PWM, a timer, a windowed watchdog, a UART, SPI and an I2C master/slave controller. The bridges and bus channel that feed them handle APB 3.0 as well.
Subsystems
Five pre-integrated subsystems for Arm Cortex-M0, Cortex-M3 and Cortex-A5 class designs. A subsystem takes bus integration off your schedule, because the interconnect, peripherals and power management already work together. Building your own topology instead? Multi-master fabrics take up to 8 masters and 12 slaves on AHB-Lite, and bridges join every pair of buses, across asynchronous clock domains too.
Delivery
Synthesizable, configurable soft IP. Cores ship as Verilog source with a complete test environment and an AXI or AHB bus functional model, so you can verify them in your own flow before they reach your top level. Subsystems add test suites, user and integration guides, and technology-independent synthesis constraints.
Where AMBA IP fits in your SoC
SoC interconnect and IP reuse
Standard AMBA interfaces, so a core you license for this program can carry over to the next one.
High-performance computing and mobile processors
AXI4 fabrics and bridges, or the AXI Performance subsystem around a Cortex-A5 class processor.
Low-power embedded and IoT designs
APB peripherals and the AHB Low-power subsystem, with power management and startup code included.
Multi-core and heterogeneous architectures
Multi-master fabrics, plus asynchronous bridges for domains running at any clock ratio.
Part numbers you can check before you call
Silvaco’s production IP has been fabricated and tested in silicon. Every AMBA part has its own
published part number, and most have a product brief.
41 parts
controllers, peripherals, fabric, bridges and subsystems, each with its own part number
5 subsystems
each one built around an Arm Cortex processor
AXI4 · AHB-Lite · APB 3.0
plus AXI4-Lite, AHB 2.0 and APB 2.0 across the range
RTL · test bench · BFM
shipped with the cores, ready to run in your own flow
Catalog · PDF
Summer 2026
IP selection guide
The AMBA cores, fabrics, bridges and subsystems by part number, alongside Silvaco's I3C and automotive networking IP.
Product brief · PDF
March 2026
AXI Performance Subsystem
An AXI4 multi-layer fabric with 8 masters and 16 slaves, built on a Cortex-A5 class processor with 4-channel DMA, SRAM and QSPI XIP controllers. Linux or RTOS, your choice.
Product brief · PDF
March 2026
Secure AHB Performance Subsystem M3
A Cortex-M3 subsystem on a secure AHB crossbar, with parameterized SRAM and ROM memory protection, power management, 4-channel DMA and a boot loader that authenticates and decrypts code from serial flash.
Product brief · PDF
March 2026
AHB Multi Fabric
Connects up to 8 masters to 12 slaves on AHB-Lite, for designs that have outgrown a single-master bus.
Tell us what's on your bus
Name the buses and the processor your SoC uses. An IP specialist will size a
configuration to your performance and area budget and walk you through subsystem
integration and licensing. If the same chip needs I3C, processor IP or Silvaco EDA
tools, that’s one vendor and one conversation.
Questions about AMBA IP
What is AMBA?
AMBA, the Advanced Microcontroller Bus Architecture, is Arm's open specification for the on-chip buses that link processors, memory and peripherals inside an SoC. AXI, AHB and APB are its best-known protocols. Silvaco's AMBA IP is built to those protocols, from a single peripheral up to a full subsystem, so your blocks meet over a standard interface.
What is the difference between AXI, AHB and APB?
AXI is the high-bandwidth interconnect, with separate read and write channels, for processors and fast memory. AHB is the system bus for DMA, memory controllers and mid-speed peripherals. APB is the simple, low-power bus for timers, UARTs and GPIO. Many SoCs run all three, which is why Silvaco offers a bridge between each pair.
Which protocol versions are supported?
Silvaco's AMBA IP covers AXI4 and AXI4-Lite, AHB 2.0 and AHB-Lite, and APB 2.0 and 3.0. The APB peripherals themselves are APB 2.0. APB 3.0 comes in through the AHB to APB and AXI to APB bridges and the APB bus channel. For any other version, ask an IP specialist.
Is the IP soft or hard?
Soft. The cores are synthesizable, configurable RTL delivered as Verilog source, so they go through your own synthesis flow on your chosen process instead of arriving as a fixed hard macro. The subsystems come with technology-independent synthesis constraints for the same reason. And the production IP itself has been through fabricated silicon.
What is an AMBA subsystem?
An AMBA subsystem is a pre-integrated set of bus fabric, bridges, peripherals and power management built around an Arm processor. You start from an interconnect that already works instead of assembling and verifying one yourself. Silvaco offers five: low-power and performance AHB designs for Cortex-M0, one for Cortex-M3, a secure M3, and an AXI design for Cortex-A5 class processors.
How is AMBA IP configured and verified?
Each core is configurable. It arrives as RTL with its own test environment and a bus functional model for AXI or AHB, which lets you check behavior in your own flow before integration. Subsystems also include test suites and an integration guide. Your area and performance targets set the configuration, and an IP specialist will work through it with you.
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