Logic and Memory
Logic and memory semiconductor solutions: TCAD and design for advanced CMOS and memory
A memory semiconductor program can’t absorb a failure first found in silicon, so Silvaco lets you model the 3D structure and verify yield across the whole memory before you commit a wafer.
A 3D problem with a yield budget counted in sigma
On an advanced CMOS or memory program, you can’t settle the process first and design the device afterward. A FinFET, a GAA nanosheet or a 3D NAND stack is a 3D object, and each etch and deposition shapes how it behaves electrically. A 2D shortcut throws away the very effects that make or break a new node.
Variation is the second problem. Every bit cell in an array is a copy of the same cell, so even a one-in-a-billion failure rate turns into lost yield. Simulate one cell or a slice, extrapolate, and you’re guessing. You need the full memory in view before silicon tells you the same thing at a far higher price.
Where Silvaco fits in your flow
Begin with the 3D structure and end with yield for the full memory. When the
question grows past one device, FTCO takes it to the fab.
Input
Your process and bit cell
The recipe, the 3D structure and the cell design
Memory semiconductor and logic
technologies covered
What Silvaco models, cell by cell and across the array.
Memory
DRAM, 3D NAND, flash and HBM, plus emerging memory such as resistive RAM (RRAM).
Victory Process etch models cut deep holes and reproduce the bowing and twisting real etches leave behind. Victory Device’s ReRAM model captures the switching physics inside the cell.
Logic
Planar and advanced CMOS, FinFETs and gate-all-around nanosheet FETs (GAAFETs).
Fins get their shape from geometric etch models, and Victory Device simulates the finished transistor in 3D. On the design side, Silvaco’s standard cells and memory compilers are built for you to tune to your chip, not take as they ship.
Yield and variation
Some bit cells have to be proven at 7 sigma or higher. VarMan gets there at up to 30X the speed of brute-force Monte Carlo.
VarMan XMA runs the entire memory through your golden SPICE simulator and estimates yield from all of it. No sampled slice, no single critical path.
Verification at array scale
When an SRAM array outgrows full SPICE, SmartSpice Pro still simulates it.
SmartDRC/LVS runs physical verification on memory designs, and Jivaro Pro reduces post-layout parasitics so sign-off simulation of a dense array stays within reach.
Applications
The work that brings memory and logic teams to Silvaco.
3D NAND and DRAM process and device development
Model deep-hole etch and the 3D stack before you run a wafer
SRAM array yield and high-sigma analysis
Find the rare failures that set yield across the whole array
FinFET and GAAFET device exploration
Compare fin and nanosheet options in 3D before you commit a process
Emerging memory research
Work up resistive RAM from its switching physics
Evidence from memory makers and research groups
Micron, Nanya and PSMC have signed multiyear agreements for Silvaco’s sign-off accepted verification, on some of the hardest process nodes in production. SK Hynix signed off HBM4E with help from capacity and performance gains in Jivaro-Pro-DX.
Customer
February 2022
Micron Technology
Widened its Silvaco partnership to co-develop FTCO digital twin models for memory and storage. It also put $5.0 million into FTCO's development.
“Silvaco’s AI and digital twin solution is enabling us to accelerate our groundbreaking advancements in memory and storage.”
Dr. Gurtej Sandhu, Principal Fellow and Vice President, Micron Technology
Research partner
February 2022
CEA-Leti
Ran VarMan XMA on an ultra-low-power 256 Kb SRAM to find its fails and estimate yield. Measured STMicroelectronics 28 nm UT-FDSOI dies tested the predictions.
Customer case study
February 2022
Mobile Semiconductor
Took its memory IP characterization to SmartSpice and SmartView, where a single 22 nm node called for 56,000 SPICE runs. Characterization times improved 50% after the switch.
Talk · SURGE 2026
February 2022
Advanced Logic FinFET/Nanosheet Simulation with Silvaco Victory Tools
Professor Zhenhua Wu, Zhejiang University, on how Victory tools model FinFETs and the GAA nanosheets that carry scaling past 3 nm.
Webinar · Emerging memory
February 2022
Resistive RAM Switching Analysis with Victory TCAD Solution
How a ReRAM model built on Victory Device's Chemistry Module explains OXRAM and CBRAM switching, for memory past the scaling limit of flash.
Webinar · FinFET and memory
February 2022
Learn How to Efficiently Achieve Accurate Experimental Etch Profiles in FinFET and Memory Applications with Victory TCAD Solution
Geometric etch models matched to measured fin and 3D NAND profiles, bowing and twisting included.
More on logic and memory
Webinar · 2025
February 2022
Utilizing Silvaco TCAD for 3D Silicon Simulation
Webinar · 2018
February 2022
Memory Statistical Characterization Solution with VarMan
Article · 2015
February 2022
Deep Hole Etching Simulation for Advanced NAND Flash Memory
Product brief
February 2022
VarMan XMA Option – Full-chip Memory Yield Analyzer
Working on a new node or memory stack?
Tell our engineers what it is and which step is holding it up. They’ll show you what changes,
using a structure or memory close to yours.
Questions from memory and logic teams
What is TCAD for memory development?
TCAD for memory development simulates how a memory device will be built and how it will behave, before a wafer runs. Victory Process grows the structure step by step in 3D, deep-hole etch and its non-ideal profiles included. Victory Device then simulates it electrically, including resistive switching in RRAM.
Why can a memory array not be qualified from one cell?
A memory repeats one bit cell across the whole array. A failure too rare to show up in one simulated cell still costs yield in silicon. A slice or critical path misses most of the memory, and the yield extrapolated from it can be off. VarMan XMA analyzes all of it instead.
Which memory technologies does Silvaco support?
Silvaco's tools cover DRAM, 3D NAND, flash, high-bandwidth memory and emerging RRAM. Silvaco has published deep-hole etch work for 3D NAND and ReRAM switching models. Its full-memory yield analysis is verified on FinFET, FDSOI and planar CMOS foundry technologies, and CEA-Leti tested it on an SRAM project.
What is high-sigma yield analysis and when is it required?
High-sigma analysis tells you whether a design holds its spec at failure rates far out in the tail, usually 4 to 6 sigma or more. You need it wherever one cell repeats many times. A memory bit cell may have to hold at 7 sigma, which brute-force Monte Carlo reaches only after billions of runs. VarMan needs far fewer.
Which tools cover advanced logic nodes?
For FinFETs, gate-all-around nanosheets and planar or advanced CMOS, Victory Process and Victory Device build the transistor in 3D and simulate it. VarMan covers variation on the same nodes. From there, SmartSpice Pro simulates circuits at array scale and SmartDRC/LVS runs physical verification.
Can Silvaco tools run alongside a foundry PDK flow?
Yes. VarMan and VarMan XMA drive whichever golden SPICE simulator you already trust, SmartSpice or third-party, using the models from your foundry kit. Nothing in your flow has to change. SmartDRC/LVS reads foundry rule decks, so ask our technical experts whether a deck exists for your node.
Related
TCAD
Process and device simulation through to SPICE model extraction
VarMan
Variation and rare-failure analysis, cell by cell
VarMan XMA
Full-memory yield, with golden SPICE
SmartSpice Pro
Fast circuit simulation for large SRAM arrays