Standard Cell
Standard cell library IP: CORE, Power Management and ECO Kits
Each Silvaco standard cell library is characterized for one named foundry process. Then it’s open to tuning, so your SoC team sets the power, speed and area trade-offs instead of inheriting ours.
What each library gives you to work with
Pick the kit, the thresholds and the cell height that suit the design. Then change what still doesn’t fit.
Library types
CORE libraries for the logic, a Power Management Kit (PMK) for power gating and multi-voltage design, and an ECO Kit on a fixed front-end pattern, for late layout changes with a minimal number of mask changes. Configurable architectures fit each library to its process. Not to be confused with Power Management IP, the LDO regulators and bandgap reference.
Vt options
Up to four thresholds per library, from RVT, LVT, HVT and ELVT. Put low-Vt cells on the critical paths and high-Vt cells everywhere leakage costs you more than speed does.
Track heights
7T, 8T, 10T or 12T, depending on the library. Short cells pack more logic into each square millimeter. Tall ones leave room for bigger transistors and stronger drive.
Foundry enablement
Libraries for TSMC, GlobalFoundries and UMC processes from 28 to 180 nm, each with foundry-qualified views. Low-power, embedded-flash and Bi-CMOS processes are on the list. Working on something else? Ask about your process.
What changes on the chip
The libraries are built to push frequency up and leakage down while holding yield. Dense layouts put more gross die on each wafer. Interconnect gets shorter too, so cost per function drops and power efficiency rises.
Find your library by foundry and node
Ten libraries, each characterized for a single foundry process.
Transistor Vts: RVT (regular), LVT (low), HVT (high), UHVT (ultra-high), ULVT (ultra-low), ELVT (extra-low).
GF is GlobalFoundries. CORE is the base library, PMK the Power Management Kit, ECO the ECO Kit. Need other
PVT corners? Custom characterization is available on request.
Where the libraries fit your design
Where compiled memory goes, on mature nodes and advanced ones alike.
Low-power SoCs for mobile, IoT and wearables
Low-leakage cells, fine-grained drive strengths and the PMK stretch the battery budget.
High-density digital blocks
Multi-bit and multi-height cells cut pin count and fit more function into the same rows.
Designs needing power gating and multi-voltage domains
The PMK supplies the power-gating cells, plus the level shifters that sit between domains.
Late-stage ECO changes
The ECO Kit's fixed front-end pattern keeps late fixes out of the base layers.
What you can verify before the first call
Match a library to your process and flow on your own, then talk to us.
10
libraries with published part numbers, 70350 to 70361
3 foundries
TSMC, GlobalFoundries and UMC
28–180 nm
GlobalFoundries 28SLP at one end, TSMC 180LP and GlobalFoundries 180 Bi-CMOS at the other
Thousands
of cells and cell variants per library, with drive strengths in fine steps
Liberty, LEF, GDSII
the views your flow reads, DRC/LVS-clean on delivery
Catalog · PDF
Summer 2026
IP product selection guide
Every standard cell library in one table: foundry, node, track height, kits, Vts, gate length and part number.
Product brief · PDF
Summer 2026
Low Power Foundation IP
The low-power library, its PMK and ECO Kit, and the low-power SRAM, feature by feature on one sheet.
Webinar
Summer 2026
Achieving Extreme Low Power IoT Designs with Silvaco’s 55LPx Foundation IP Solution
Low-power foundation IP on GlobalFoundries 55LPx, the process behind libraries 70353 and 70354. Aimed at IoT parts that have to last three to five years on one battery.
News
Summer 2026
Silvaco acquires memory compiler technology of Dolphin Design SAS
The deal brought Dolphin Design's standard cell libraries to Silvaco along with its memory compilers.
Bring us your node and your PPA targets
Name the foundry and node, and what the design has to hit. An IP specialist will tell
you which library fits and what it takes to tune one that nearly does. You’ll also hear
how licensing and evaluation work.
Standard cell library questions
What is a standard cell library?
It's the set of pre-designed logic cells, from simple gates to flip-flops and multiplexers, that synthesis and place-and-route tools assemble into a digital block. Each cell arrives characterized for timing and power on one process. Silvaco supplies CORE libraries with optional Power Management and ECO Kits, delivered as Liberty, LEF and GDSII views.
What are Vt options and why do they matter?
Vt is the threshold voltage at which a transistor turns on. Lower-Vt cells switch faster and leak more; higher-Vt cells leak less and switch slower. Mixing them lets you spend leakage only on the paths that need the speed. Silvaco libraries carry up to four Vt flavors, depending on the process.
What is track height?
Track height is a cell's height counted in routing tracks, the metal pitches that fit across it. Fewer tracks give you denser logic. More tracks leave room for larger transistors and stronger drive. Silvaco's libraries come in 7T, 8T, 10T and 12T, set library by library.
What is an ECO kit?
An ECO kit holds cells laid out on a fixed front-end-of-line pattern. A bug found after layout is fixed by reconnecting those cells. Only a few masks change, not the whole set. Four of the ten Silvaco libraries in the catalog include one.
Which foundries and nodes are available?
Ten libraries cover GlobalFoundries 28SLP, 55LPx (0.9 V and 3.3 V), 130LP and 180 Bi-CMOS; TSMC 40LP, 65LP, 110LP and 180LP; and UMC 55LPeFLASH. That spans 28 to 180 nm. If your process isn't among them, an IP specialist can tell you whether a custom characterization makes sense.
Can a library be customized for a process?
Yes, two ways. Silvaco can configure the architecture and add custom PVT corners, low-voltage operation included, on request. Or your team tunes it directly. CellForge 2D adjusts transistor sizing, row height and DFM rules across a whole library. LibertyForge LC then recharacterizes the result into Liberty timing and power models.
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