Interface IP
Interface IP: general-purpose I/O and high-speed LVDS
Silvaco interface IP for your SoC’s I/O ring: a general-purpose I/O library and a silicon-proven 2 Gbps LVDS transceiver, verified before they reach your integration flow.
What's in the libraries
Most pins need general-purpose I/O. The fast ones, and the
ones bound to a standard, need something more specific.
LVDS high-speed I/O
A transmitter and receiver pair for differential links at up to 1 GHz and 2 Gbps. Pre-emphasis is programmable, PVT compensation is built in, and on-chip termination with common-mode support on both RX and TX means you don’t place termination resistors off-chip. Silicon proven and DFT compliant, with 2 kV HBM ESD.
General-purpose I/O
Universal GPIO IP for the rest of your pins. You set drive strength and slew rate. The Schmitt trigger and ESD protection are already in the cell, and SSO noise analysis ships documented.
Specialty I/O
Some pins need one particular standard, or have to work somewhere unusual. Alongside LVDS, Silvaco offers SSTL, the stub-series terminated logic that DDR memory interfaces run on, and I/O built for cryogenic applications. Ask an IP specialist for the specifications on your process.
Looking for the LVDS PHY?
Same four letters, different product. Silvaco’s LVDS I/O is transmitter and receiver cells at the pad. Mixel, a Silvaco company, licenses LVDS serializer and deserializer PHYs for moving parallel data over serial links. If that’s what you need, go to LVDS. Mixel’s MIPI PHYs sit in the same family.
Where these libraries fit
Chip-to-chip high-speed links
Differential LVDS signaling at up to 2 Gbps between devices on the board
Display and imaging interfaces
LVDS I/O driving displays, printers and similar high-speed data paths
General SoC I/O rings
The bulk of the pad ring, tuned through programmable drive strength
Automotive and industrial temperature ranges
−40 to 125 °C operation on the LVDS I/O
Published figures and deliverables
Silvaco builds its interface cores to be foundry-agnostic, and the
LVDS I/O is silicon proven.
2 Gbps
LVDS data rate, at up to 1 GHz
2 kV HBM
ESD rating on the LVDS I/O
−40 to 125 °C
LVDS I/O operating range
IBIS · LEF · GDSII
Delivered with timing data and a datasheet
Product brief · PDF
Summer 2026
LVDS I/O IP high frequency transceiver
Highlights, deliverables and operating range for the LVDS I/O, on one page.
Check it against your process
Tell an IP specialist your foundry, your node and the pins you have to cover. You’ll
get performance, area and power figures for that process, plus a straight answer on
availability. Licensing terms come up in the same conversation, and if you want
to see how these cells sit next to Silvaco’s controller and PHY IP, ask for a technical briefing.
Interface IP questions
What is interface IP?
Interface IP is the licensed circuitry that moves signals on and off a chip. At the pad, that means I/O cells such as Silvaco’s general-purpose I/O and 2 Gbps LVDS, each with ESD protection. Further up the stack sit PHYs from Mixel and bus controllers such as AMBA and I3C, both covered under Design IP.
What is the difference between GPIO and specialty I/O?
General-purpose I/O covers most of a chip's pins, with programmable slew rate and drive strength, ESD protection and a built-in Schmitt trigger. Specialty I/O is built for one job: high-speed LVDS at up to 2 Gbps, SSTL for DDR memory interfaces, or I/O that works at cryogenic temperatures.
How does this LVDS differ from the Mixel LVDS PHY?
The difference is the layer. On the I/O side you license the pad cells themselves, with pre-emphasis, built-in termination and ESD protection, for links up to 2 Gbps. Mixel's LVDS IP is a PHY: four-channel serializers and a deserializer that convert between parallel and serial data, listed at 700 to 1000 Mbps depending on the part and process.
What ESD protection is provided?
The LVDS I/O is rated to 2 kV on the human body model (HBM). The general-purpose I/O includes ESD protection as well. Its level depends on your process and pad configuration, so confirm the rating for your design before you commit to a pad ring.
What temperature range is supported?
Silvaco rates the LVDS I/O for −40 °C to 125 °C, which covers industrial designs and many automotive ones. For the general-purpose I/O's range, or an automotive qualification grade on either library, talk to an IP specialist with your application in hand.
What data rates does the LVDS I/O reach?
Up to 2 Gbps, with the LVDS I/O running at up to 1 GHz. The transmitter's pre-emphasis is programmable, so you can tune the signal to the channel it drives, and a compensation block keeps it PVT-invariant. Full performance, area and power specifications come on request.
Related IP
LVDS
Mixel serializer and deserializer PHY IP
LVDS Serializer
Mixel transmit-side LVDS PHY
LVDS Deserializer
Mixel receive-side LVDS PHY
Standard Cell
CORE, PMK and ECO libraries, 28 to 180 nm
Foundation IP
Standard cells, memory compilers and interface IP