AI-Driven Design
Electronic design automation software and silicon IP
AI-Driven Design is Silvaco’s electronic design automation and licensed IP: circuit simulation, custom layout and verification, plus the interface and foundation blocks you’d rather license than draw.
Pick the family that fits the job
Simulating a circuit, drawing and checking it, and licensing proven silicon are different jobs. Each gets its own set of EDA tools.
Circuit Simulation
SPICE simulation, plus the power, EM/IR and thermal analysis that shows whether your supply network holds up under load.
Circuit Simulation
Schematic to layout, with verification, extraction and variation analysis in between. A DRC error or parasitic problem shows up while you can still move a polygon.
Design IP
Silicon you don’t have to design yourself. Mixel MIPI PHYs proven at nine foundries, plus standard cells, memory compilers and system IP you can tune.
Fits the flow you already run
Covers
Schematic capture through layout, physical verification, extraction and post-layout simulation for analog, mixed-signal and custom IC.
DRC, LVS and physical verification, inside the layout editor.
The whole parasitic chain — extract with Hipex, reduce with Jivaro Pro, analyse with Viso, compare decks with PEX Certify.
SPICE simulation at production scale, with the Verilog-AMS 2.3.1 analog subset for behavioural models.
Licensed silicon — MIPI interface PHYs, standard cell libraries, memory compilers and system blocks.
Does not
Do digital implementation. There is no synthesis and no place-and-route here — nothing in this portfolio takes RTL and produces a placed, routed block.
Ask you to abandon a sign-off deck you are already qualified on. Expert links to Calibre RealTime for sign-off quality DRC on demand, and is integrated with Calibre Interactive and Calibre RVE.
Require Silvaco extraction to do it. Jivaro Pro is independent of the tools either side of it and reads DSPF, SPEF, SPICE3, HSPICE, Spectre and Calibre View.
Need your decks rewritten. SmartSpice is HSPICE and Spectre compatible, so an existing deck runs as it is.
Originate the device models you simulate against. Those come from the foundry PDK, or from the manufacturing side via characterization and extraction.
What crosses the boundary
| TOOL | FORMATS IN AND OUT | THIRD-PARTY INTERFACES |
|---|---|---|
| Gateway Schematic | SPICE, CDL, NDL, Verilog IEEE 1364, OpenAccess, iPDK | EDIF 2 0 0 to third-party schematic tools; drives HSPICE® as well as SmartSpice |
| Expert Layout | GDSII, LEF/DEF, DXF, OASIS, CIF, Applicon, OpenAccess | Calibre® RealTime, Calibre Interactive and Calibre RVIE; imports existing Virtuoso technology-file information |
| SmartSpice Simulation | HSPICE® and Spectre® netlists and models; Verilog-AMS 2.3.1 analog subset | Runs an existing HSPICE or Spectre deck without a rewrite |
| Hipex Extraction | In: GDSII, cell netlists, rule-based technology files | Back-annotates the schematic netlist with the extracted parasitics |
| Jivaro Pro Reduction | DSPF, SPEF, SPICE3, HSPICE®, SPECTRE®, Calibre® View, OpenAccess | Independent of the extraction and simulation tools either side of it |
HSPICE and Spectre are registered trademarks of Synopsys and Cadence Design Systems respectively; Calibre is a registered trademark of Siemens EDA. Named here to state compatibility, not affiliation beyond the published EDA partnerships.
Days back on post-layout simulation
Design teams at 6 of the 10 largest semiconductor companies use Silvaco EDA software. Two customers timed their post-layout runs before and after Jivaro Pro.
20+ days → 6 days full simulation of one block, post-layout
"…a full simulation on one of our blocks would run 20+ days. After using Jivaro Pro this runtime was reduced to 6 days while maintaining the designer's accuracy requirements."
eTopus
Harry Chan, Founder and CEO
At least 5× shorter post-layout SPICE runtimes at 40nm and 55nm
Yasuyuki Hattori, Senior Manager of IC Engineering
Alps Alpine Co., Ltd
Yasuyuki Hattori, Senior Manager of IC Engineering
Release and version index
Current versions across the design portfolio, from the 2025 baseline release.
What crosses the boundary
| FAMILY | PRODUCT | CURRENT VERSION | RELEASE DATE |
|---|---|---|---|
| Circuit Simulation | SmartSpice Includes RF and Pro | 5.9.2.R | Not published |
| SmartView Waveform Viewer | 3.2407.01R | Not published | |
| SmartSpice RealHard - Circuit Rubberband | Part of the SmartSpice suite | Not published | |
| Analog and Custom IC | InPar Power EM/IR/Thermal | Not in the baseline release | Not published |
| Gateway Schematic editor | 4.2407.01R | Not published | |
| Expert Layout editor | 5.2407.01R | Not published | |
| SmartTools DPC, LVS and RCE | 1.2407.01R | Not published | |
| Hipex Full-chip parasitic extraction | 4.2407.01R | Not published | |
| VarMan Variation and yield | 2023.11.3R | Not published | |
| Jivaro Parasitic reduction | 2025.12.5.R | Not published | |
| VIVA Netlist analysis | 2025.2.10.R | Not published | |
| PEX Diff - PEX Link Extraction comparison | 2025.3.17.R | Not published | |
| Design IP | Mixed PHY IP - Foundation and system IP | Not on a software release cadence | Per process and node |
Silvaco does not support virtual machines as licence servers, and does not publish release dates. Versions are revised through the year.
Where your device models come from
AI-Driven Manufacturing is Silvaco’s process and device side: TCAD, Lithography, Plasma and Photonics, plus FTCO. Utmost IV turns device data into SPICE models, and Victory RCx pulls parasitics out of TCAD’s simulated 3D structures. That hand-off matters most when your node is too new for a mature model library.
Test it on a block you already know
Send a netlist or layout whose behavior you’ve already measured. An application
engineer runs it on the tools that match, and you check the result against numbers you trust.
Before you shortlist anything
What does Silvaco offer for analog and custom IC design?
Everything between the schematic and sign-off, licensed tool by tool. You capture in Gateway, lay out in Expert, and run DRC and LVS on the layout. Extraction, parasitic reduction, netlist analysis and variation tools follow, and each one fits into your existing electronic design automation flow.
Is Silvaco a realistic alternative to Cadence Virtuoso?
It depends on how much of your current flow you want to keep. Expert imports your existing Virtuoso technology-file data, handles OpenAccess in both directions, and hands off to Calibre RealTime for sign-off DRC. The fair test is one of your own blocks, on your own layers.
Can a small design team afford this toolset?
Yes, because you license tools one at a time, with updates and support included. Time-based licenses run one, two or three years per tool and float from a server across your network. Pricing isn't published, so ask about the one tool your team needs first.
Can I use Silvaco tools alongside Cadence or Synopsys tools in the same flow?
Yes, and Cadence, Siemens EDA and Synopsys are all Silvaco EDA partners. SmartSpice takes your HSPICE and Spectre decks as they are, and Expert moves layout as GDSII, OASIS, LEF/DEF or OpenAccess. Jivaro Pro reduces DSPF, SPEF and Calibre View parasitics from any extractor.
What semiconductor IP does Silvaco license?
Two groups, one of them built by Mixel's MIPI team since 1998. Mixel PHY IP spans MIPI D-PHY, C-PHY, CSI-2 and DSI, proven in silicon on twelve nodes from nine foundries. Foundation and system IP adds standard cells, SRAM, ROM and register-file compilers, and AMBA, I3C and automotive blocks.
Which foundries and PDKs are supported?
Seven foundries partner with Silvaco: ams AG, GlobalFoundries, ON Semiconductor, TSMC, Tower Semiconductor, UMC and X-FAB. What's supported depends on the process node, and the published PDK table lists a sample of it. If your node isn't in it, ask before you plan an evaluation.
How does the design portfolio connect to Silvaco manufacturing tools?
Through two kinds of file your circuit flow already reads. Utmost IV writes SPICE models that Eldo, HSPICE, LTspice, QSpice, SmartSpice and Spectre can read. Victory RCx supplies parasitics from a simulated 3D structure, so either one feeds the simulator you already run.
How do I evaluate the portfolio?
With your own design, not a download, because there's no self-serve trial. You run a licensed evaluation on your hardware and data, with an application engineer alongside. The Evaluation License Agreement and mutual non-disclosure agreement that govern it are published, so your legal team can read them first.