Low Power Foundation IP
Low Power Foundation IP: standard cells and memory for energy-efficient design
Low power foundation IP for ASIC and SoC teams building battery-powered and always-on chips: low power standard cell libraries, power management and ECO kits, and low-leakage SRAM, tuned to your power budget.
Low power standard cells and SRAM
you tune to the target
A wearable’s power budget isn’t an accelerator’s, so no single setting fits both. Stack the
techniques your design needs across cells and memory, and the savings compound.
Thresholds, wells and cell choice
Around 650 regular standard cells, plus more than 150 built for low power or high speed. Most come in five threshold voltages, in twin- or triple-well versions. Fine drive-strength steps and multi-bit, multi-height cells give synthesis the right size of cell instead of an oversized one. Each cell is also optimized for routability and yield, not just power.
Power gating, voltage domains and late fixes
A Power Management Kit for power gating and multi-voltage design, with level shifters for multiple voltage domains. An ECO kit on a fixed pattern for the front-end-of-line layers, for late layout changes with the fewest mask changes. Not to be confused with Power Management IP, the LDO regulators and bandgap reference.
Memory that powers down in segments
The SRAM embeds its own power switches, with retention switches as an option, so you don’t design them into the SoC. Segmented power control shuts off parts of the array on their own, and a transition ramp controller cuts the inrush current when they come back.
Low-voltage operation
Read and write assist keep the SRAM working as the supply drops. Its periphery mixes threshold voltages to hit your PPA target, and a single-supply option keeps integration simple. Need a low-voltage corner? The cells and the memory can both be characterized for one.
Sleep modes for the SRAM
Nap, Retention, Nap + Retention and shut-down step leakage down in turn, each trading a slower wake-up for the saving. Shut-down goes lowest and gives up the data. Nap and Retention modes are offered at 55 nm, 40 nm and below.
Designs where power sets the limit
Battery-powered and energy-harvesting designs
Leakage decides how long the battery lasts, or whether harvested energy covers the load at all.
IoT and wearables
Devices expected to run three to five years on one battery, asleep most of that time.
Always-on subsystems
Logic and memory that keep running while power gating shuts the rest of the chip down.
Designs with multiple voltage domains
Each block runs at the voltage it needs, with level shifters at the boundaries and power gating per block.
Published leakage data and named processes
Silvaco’s low power IP is in volume production, with tapeouts at several customers behind it.
0.28×
stand-by leakage in Nap + Retention, 4Kx32 SRAM instance
650 + 150
regular cells, plus cells for low power or high speed
5 Vts
on most cells, in twin or triple wells
1.2 V · 0.9 V
domains, bridged by level shifters
High sigma
Variation analysis for yield, run in VarMan XMA
| MODE | LEAKAGE VS STAND-BY | WAKE-UP |
|---|---|---|
| Stand-by | 1× | Fastest |
| Nap | 0.65× | About one clock cycle |
| Retention | 0.54× | Slower, while the periphery powers back up |
| Nap + Retention | 0.28× | Slower, while the periphery powers back up |
| Shut-down | Lowest, and the data is lost | Slowest |
Figures for a 4Kx32 instance: typical process corner, 1.2 V, 25 °C.
Four catalog libraries ship with the core library, the Power Management Kit and the ECO kit together.
| PART NUMBER | FOUNDRY | PROCESS | VOLTAGE (V) | TRACK HEIGHT | LIBRARIES |
|---|---|---|---|---|---|
| 70350 | GlobalFoundries | 28 nm SLP | 0.9 | 8T | CORE, PMK, ECO |
| 70353 | GlobalFoundries | 55 nm LPx | 0.9 | 7T | CORE, PMK, ECO |
| 70357 | TSMC | 110 nm LP | 1.2 | 7T | CORE, PMK, ECO |
| 70360 | TSMC | 180 nm LP | 1.8 | 7T | CORE, PMK, ECO |
PMK: Power Management Kit. Working on another process? An IP specialist will tell you what’s characterized there.
Product brief · PDF
Summer 2026
IP product selection guide
Cells, SRAM, the leakage chart and the four cell-level power strategies, on two pages.
Webinar
Summer 2026
Achieving Extreme Low Power IoT Designs with Silvaco’s 55LPx Foundation IP Solution
How Silvaco's low power cells and memory compilers extend battery life on GlobalFoundries 55LPx, the process behind library 70353.
Webinar
Summer 2026
How to Design Ultra-low Power Embedded Memories with Silvaco Memory Compilers
Check your node and power target with an IP specialist
Check your node and power
target with an IP specialist
Missing a power target shows up at silicon, and a re-spin costs far more than a
conversation now. Tell an IP specialist your foundry, node and power budget. You’ll hear
what’s characterized there and how licensing works. There’s also a 30-day evaluation, with
a front-end and LEF kit, so your team can run PPA analysis on its own design
first.
Low power foundation IP questions
What makes an IP library low power?
Several techniques, stacked. The cells come in multiple threshold voltages and well options, long-channel cells cut static power, and drive strengths are fine enough that synthesis doesn't oversize. Power gating shuts idle blocks down, level shifters split voltage domains, and the SRAM adds Nap and Retention modes to cut leakage.
What is a Power Management Kit?
A Power Management Kit extends a library for designs that switch blocks off or run several supplies. It adds power-gating cells, plus level shifters between 1.2 V and 0.9 V domains. Four Silvaco libraries offer one: GlobalFoundries 28 nm and 55 nm, TSMC 110 nm and 180 nm. Regulators sit in the separate Power Management IP family.
What is an ECO kit and when is it used?
Late in a project, once the base layers are frozen. Every cell in an ECO kit shares one fixed front-end-of-line pattern, so a late engineering change order goes through with the fewest possible mask changes. All four Silvaco libraries with a Power Management Kit include an ECO kit too.
What are read and write assist?
They're circuit techniques that keep an SRAM bitcell reading and writing reliably as the supply voltage drops. That matters because lower voltage is where most of the power saving sits. Silvaco's low power SRAM includes both, with a multi-threshold periphery tuned to your power, performance and area target.
How does this relate to the standard cell and memory pages?
Low Power Foundation IP is the power-first set from both catalogs. It covers the libraries that carry a Power Management Kit and an ECO kit, plus the SRAM with its low leakage modes. To choose a library by foundry, node or threshold voltage, use the Standard Cell selector. For SRAM, register file and ROM compilers, use the Memory Compilers selector.
Can characterization corners be customized?
Yes. Custom characterization corners are available for the standard cells and the SRAM, low-voltage operation included, and custom PVT characterization is available on request. You can also try a corner on your own design during the 30-day evaluation, before you license.
Related IP
Standard Cell
CORE, Power Management Kit and ECO libraries, with the library selector
Memory Compilers
SRAM, register file and ROM compilers, with the compiler selector
Foundation IP
Standard cells, memory compilers and interface IP
Design IP
Every Silvaco IP family, from MIPI interfaces to embedded processors