Viso
Viso: Schematic Viewer for SPICE Netlist Files
Load a parasitic netlist and see which nets the layout is hurting, and why, before you queue a long post-layout simulation.
Parasitic analysis straight from the netlist
Viso is Silvaco’s parasitic analysis tool for RC networks. Give it a parasitic netlist and it shows you where the extracted resistance and capacitance are costing the design. Crosstalk, weak signals, unbalanced net symmetry, delay degradation, IR drop: each one traced to its cause. You get that answer from the netlist alone, with no simulation in the loop.
What you can measure, explore and check
Start with one metric across every net. Then drill down, layer by layer, to the RC segment that’s causing it.
Analyses
Measure crosstalk, signal weakness, RC delay, net symmetry and IR drop, plus pin-to-pin and access resistance, voltage maps and complex impedance. Compare nets directly, differential and parallel pairs included.
Point and click for an equivalent resistance or RC delay on the spot. Sanity checks flag shortcuts and disconnected instances within seconds.
Exploration
Test a fix on the parasitics first. Remove, add or re-value a resistor or via, or change a whole layer’s resistivity, then rerun the analysis without touching the layout.
Viso marks the elements driving each result on the layout itself. Overlay GDSII or OpenAccess data on the parasitics, and merge multi-finger pins with initial conditions you choose.
Power networks
Load the full power network, however large. Map resistance, delay and voltage drop across it for debug or what-if exploration. Skip the power simulation you’d otherwise wait on.
Capacity and interfaces
Parasitic netlists above 100 GB and very large power nets both load, and render in 2D and 3D.
Viso links to Cadence Virtuoso. Every analysis also runs from the command line. The checks you trust in the GUI become batch verification scripts on every project.
Formats
Reads: DSPF, SPEF and SPICE parasitic netlists, CalibreView parasitic netlists, OpenAccess extracted views.
Writes: ASCII CSV and TSV results, plus a results database you explore in the GUI.
Runs on: Red Hat Enterprise Linux 7.9 and 8.x, and SLES12 SP5, x86_64.
Where Viso sits in your flow
Viso checks parasitics at two points. Early extractions, while the layout is still short
of LVS-clean. And the sign-off extraction, ahead of simulation.
Takes in
A parasitic netlist, and nothing else. DSPF, SPEF, SPICE or CalibreView, or an OpenAccess extracted view, from Hipex or a third-party extractor.
Hipex: Silvaco’s full-chip parasitic extractor, in the same flow
Hands off to
Whichever tool acts on what you found.
PEX Certify: when the fault is in the extraction flow itself
Jivaro Pro: to reduce the network after you’ve diagnosed it
Expert: to fix the layout
What you'd use it for
Finding layout problems before simulation
Pinpoint the problem net and weigh the fixes while the layout can still change.
Power network debug and exploration
Resistance, delay and voltage-drop maps across the whole grid.
Crosstalk and signal integrity checks
Coupling, symmetry and delay on high-speed nets, without rerunning a long simulation after every change.
Screening designs too big to simulate
Analyses fast enough for the largest designs you have.
Datasheet, slides and talks
The datasheet has the specs. The talks show the analyses running on real circuits.
Product brief · PDF
February 2022
Viso – Parasitic Analyzer and Debugger
Every analysis, input and output format, and supported platform, on two pages.
Presentation · PDF
February 2022
Viso – Parasitic Analysis and Debug
The top-down method from a whole-net metric to a single RC segment, plus what-if edits and the Virtuoso link.
Webinar
February 2022
Using Viso to Investigate, Analyze, and Solve Complex Parasitic Issues
Root-causing parasitic problems on a high-speed LVDS block, from first symptom to fix.
Conference talk
February 2022
Using Viso to Investigate, Analyze and Solve Advanced Parasitics Issues
Timing estimates, crosstalk and net matching used to pinpoint trouble spots in high-speed circuits.
Conference talk
February 2022
Latest Update on Interconnect Parasitic Reduction and Analysis with Jivaro and Viso
The Viso features added for debugging parasitic structures without long simulation runs, alongside Jivaro's reduction updates.
Webinar
February 2022
Advances in Parasitic Pro Reduction and Analysis with Jivaro and Viso
Parasitic reduction with Jivaro and analysis with Viso, in one session.
Documentation
February 2022
Viso documentation
Manuals and release notes, in Support and Downloads.
Try it on the netlist that's giving you trouble
Send a parasitic netlist from a block that isn’t meeting its targets. An application engineer runs
Viso on it with you and shows where the layout is causing the problem.
Questions about Viso
What is parasitic analysis?
Parasitic analysis examines the resistance and capacitance a layout adds to a circuit and finds where they hurt performance: crosstalk between nets, weak signals, broken symmetry, extra delay and IR drop. Viso runs it directly on the extracted netlist and marks the elements responsible on the layout, so you know what to fix.
Can Viso work without running a simulation?
Yes. Viso needs only a parasitic netlist and computes resistance, RC delay, crosstalk, net matching and voltage drop straight from it, with sanity checks that finish in seconds. Screen a design and test what-if fixes ahead of any long post-layout run, even while the layout isn't LVS-clean yet.
Which parasitic netlist formats does Viso read?
Viso reads parasitic netlists in DSPF, SPEF, SPICE and CalibreView formats, plus OpenAccess extracted views. That covers the output of Silvaco's Hipex and of third-party extractors. Results come out as ASCII CSV or TSV files for your scripts, and as a database you can explore in the GUI.
How large a netlist can Viso handle?
Viso takes parasitic netlists of more than 100 GB, along with very large power nets, and draws the network in 2D and 3D. Its analyses run fast enough for designs considered too large to simulate, in batch from the command line or interactively in the GUI.
Does Viso work with Cadence Virtuoso?
Yes. Viso reads Virtuoso's OpenAccess data to create its parasitics view, then keeps a direct link between your layout or extracted view and the matching Viso database. Virtuoso mirrors the layer navigation and visibility changes you make in Viso, so you explore the layout and its parasitics together.
What is the difference between Viso and a parasitic extraction tool?
An extraction tool such as Hipex calculates the parasitics from the layout and writes them to a netlist. Viso picks up that netlist and tells you what it means for the design: which nets are weak, coupled, unbalanced or slow, and where on the layout the cause is.
The rest of the TCAD suite
Hipex
Extracts the parasitic netlist Viso reads
Jivaro Pro
Reduces the network once you've found the problem
PEX Certify
Compares extracted netlists to qualify your extraction flow
Analog and Custom IC
Every tool from schematic to sign-off, nine products in all