SURGE Virtual Event North America 2025
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Concluded event
SURGE Virtual Event North America 2025
North America · Wednesday, January 15, 2025 · Virtual event
At a glance
January 15, 2025
Date
North America
Region
Virtual
Format
20
Sessions in 3 tracks
About this event
On January 15, 2025, SURGE North America 2025 put 20 talks online in a single day.
SURGE exists so the engineers who use Silvaco tools can compare notes, with each other and with Silvaco. This edition gave the floor to Ciena, Silicon Creations and SilTerra, and to researchers from Stanford and TU Wien. Silvaco’s engineers covered the rest, from the CEO keynote down to a 3nm LDO.
Date
- General Session
- Semiconductor Process and Device Track (TCAD)
- IC Design Track (EDA and IP)
Agenda
Recordings for all 20 SURGE North America 2025 talks sit on Silvaco’s support site. To open
one, sign in there or complete a short form with a work, university or government email.
General Session
Keynote
Babak Taheri, Chief Executive Officer and Director, Silvaco
Speaker bio, January 2025
AI Takes EDA to the Next Level
Wally Rhines, President and CEO of Cornami and Silvaco Board Member
Speaker bio, January 2025
Semiconductor Process and Device Track (TCAD)
TCAD Update
Dr. Eric Guichard, SVP and GM of TCAD Business Unit, Silvaco
Abstract
Speaker bio, January 2025
Products: TCAD
NanoHub Workforce Development
Dr. Peter Griffin, Stanford University
Speaker bio, January 2025
Low-temperature Behavior in Nanowire Transistors by Quantum Transport Simulation
Sanam Moslemi-Tabrizi, Analog Engineer, Ciena
Abstract
Speaker bio, January 2025
Products: Victory Atomistic
Machine Learning for Multi-Scale Plasma Process Integration and Optimization
Associate Professor Dr. Lado Filipovic, TU Wien
Abstract
Speaker bio, January 2025
Products: Victory Analytics · Victory DoE
How to Utilize Victory Analytics and Machine Learning to Calibrate TCAD Data
Dr. Stefania Carapezzi, Field Applications Engineer, Silvaco
Abstract
Speaker bio, January 2025
Products: Victory Analytics · Victory DoE
Applying Artificial Intelligence in Fab Technology Co-Optimization
Dr. Christian Caillat, TCAD Senior Staff FAE, Silvaco
Abstract
Speaker bio, January 2025
He joined Silvaco in Boise in June 2023. Before that he spent 13 years at Micron, where he led the 3D NAND cell team and worked on the emerging-memory program with imec. His PhD in microelectronics is from Grenoble INP.
Products: FTCO
Utilizing Physics-Based AI-Powered Digital Twins to Accelerate Design Optimization and Manufacturing Yield of SiC Power Devices
Dr. David Green, TCAD Applications Engineer, Silvaco
Speaker bio, January 2025
Power Devices SPICE Modeling with a Detailed SiC DMOS Parameter Extraction Methodology
Dr. Bogdan Tudor, Head of Modeling, Silvaco
Abstract
Speaker bio, January 2025
Products: FTCO
IC Design Track (EDA and IP)
EDA and IP Updates
Ben Louie, VP and GM of IP Business Unit, Silvaco
Abstract
Speaker bio, January 2025
Products: Analog and Custom IC
EDA Solutions for Physical Design of Discrete Power Devices
Stefano Pettazzi, Staff Applications Engineer, Silvaco
Abstract
Speaker bio, January 2025
Products: Expert · SmartDRC/LVS
Accelerating the Verification of High-Frequency Analog Mixed-Signal Components via Jivaro Pro Advanced Parasitic Reduction
Chung-Chun Chen, Director of Analog Design, Silicon Creations
Speaker bio, January 2025
Products: Jivaro Pro
Using Viso to Investigate, Analyze and Solve Advanced Parasitics Issues
Carlos Berlitz, Corporate Applications Engineer, Silvaco
Abstract
Speaker bio, January 2025
Products: Viso
Standard Cells Characterization Challenges and Improvement
Siti Mariyam, IP Design Enablement, SilTerra
Abstract
Speaker bio, January 2025
Products: Standard Cell
Standard Cell Library IP in Advanced FinFET Nodes for Low Voltage Applications
Fernando Carrion, Design Engineer, Silvaco
Abstract
Speaker bio, January 2025
Products: Cello FinFET
Advanced Node Library Development with Cello FinFET
Felipe Bortolon, Engineering Manager IP, Silvaco
Abstract
Speaker bio, January 2025
Products: Cello FinFET
Bandgap References for Low Voltage Operation
Ahmad S. Mazumder, Director of Engineering, Silvaco
Abstract
Speaker bio, January 2025
LDO For Low Voltage Operation
Shaikh A Shams, Staff Engineer, Silvaco
Abstract
A capless LDO designed in TSMC’s N3P 3nm FinFET process. The key figures:
- Load current: up to 30 mA
- Input: 1.2 V ±10%
- Output: programmable, 0.45–0.9 V in 50 mV steps
- PSRR: >40 dB at 1 kHz, >29 dB at 10 MHz, across all PVT corners (-40°C to 125°C)
- Load transient: <18 mV undershoot or overshoot for a 1 A/ns step, across the same corners
- Area: <3,400 µm²
Speaker bio, January 2025
Introduction to CAN-XL
Mauricio Brochi, Director of Automotive IP, Silvaco
Abstract
Speaker bio, January 2025
Products: Automotive IP
Themes at SURGE North America 2025
From SiC digital twins to DRC on curved discrete-device layouts
Victory Atomistic for quantum transport, machine learning for plasma etch, and the TCAD update
SilTerra on characterization, then two Silvaco talks on FinFET libraries
The FTCO flow, plus TCAD calibration with Victory Analytics and Victory DoE
Expert and SmartDRC on power layouts, Jivaro Pro and Viso on parasitics