Mixel-IP
Mixel Interface IP
Silicon-proven on 13 nodes at 9 foundries. Each card links to its product table below.
MIPI D-PHY
Sends data on up to four lanes with a forwarded clock lane, carrying CSI-2 camera and DSI display traffic. Up to D-PHY v3.6, backward compatible with earlier versions, at up to 6.5 Gbps per lane.
MIPI C-PHY
Encodes data in the state transitions of a three-wire trio, providing 2.28 bits per symbol. That gives high throughput at a lower symbol rate, which improves power, performance and area as data rates increase. Up to C-PHY v2.1, backward compatible with earlier versions, with up to three trios at up to 8.0 Gsps per trio (18.24 Gbps).
MIPI M-PHY
A high-speed serial PHY with an embedded clock and multiple speed gears, carrying UFS storage and UniPro chip-to-chip links. M-PHY v4.1, HS-G1 to HS-G4, up to 11.66 Gbps.
C-PHY/D-PHY combo
One PHY that supports both C-PHY and D-PHY on shared pins, reusing D-PHY circuitry to save area and leakage. Up to C-PHY v2.1 and D-PHY v3.6, backward compatible with earlier versions, at up to 8.0 Gsps per trio and 6.5 Gbps per lane.
LVDS
LVDS transmitters and receivers, plus an LVDS/D-PHY combo that drives LVDS or MIPI D-PHY displays from one PHY.
ASA Motion Link
Automotive SerDes Alliance PHY for high-speed in-vehicle camera and display links. ASA Motion Link v2.1 at up to 8.0 Gbps per lane.
Where Mixel IP is used
Edge AI and vision
On-device AI processors in smart cameras, robotics, drones and industrial machine vision act on data where it’s captured. Image sensors, LiDAR, radar, time-of-flight depth sensors and event-based vision sensors stream that data over MIPI CSI-2, carried by D-PHY, C-PHY or the C-PHY/D-PHY combo.
Automotive
IoT and wearables
Smart home cameras, video doorbells, AR/VR headsets, smart glasses and other battery-powered devices need camera and display links that sip power. D-PHY, C-PHY and the C-PHY/D-PHY combo carry MIPI CSI-2 and DSI with low-power modes and few pins.
Mobile
Camera and display links to the application processor over CSI-2 and DSI, using D-PHY, C-PHY or the C-PHY/D-PHY combo. UFS storage over M-PHY.
Industrial and display
Display panel links over LVDS, with the LVDS/D-PHY combo for designs that need to drive either LVDS or MIPI DSI displays.
Proven in silicon
Mixel IP is silicon-proven on 13 nodes at 9 foundries, and Mixel was the first IP provider to
demonstrate silicon-proven MIPI D-PHY, MIPI C-PHY and MIPI M-PHY.
Available now as PRO IP
TSMC · N5 to 90LP
N2P to 90LP, including N5, N6, N7.
GlobalFoundries
12LP+, 22FDX and 22FDX+
Samsung, SMIC, Tower and UMC
Samsung 28FDSOI, SMIC 28HPC+, Tower 65ISC/BSB, UMC 22ULL/ULP and 28HPC+, and more
STMicroelectronics
28FDSOI and 40LP
Customer · MIPI D-PHY
November 2025
indie
indie's automotive radar processors integrate ASIL-B ready Mixel MIPI D-PHY CSI-2 transmitter and receiver IP, delivered with a safety manual.
CATALOG PDF
SURGE 2025
PRO IP Product Selection Guide
Every PRO IP product with its foundry, node and part number.
Press release
Summer 2026
Mixel MIPI C-PHY/D-PHY combo IP on TSMC N2P
The first combo IP to support D-PHY v3.6 embedded clock mode, now available on TSMC N2P.
Press release
Summer 2026
Silvaco Announces Immediate Availability of Production Ready Mixel MIPI PHY IP
Mixel D-PHY, C-PHY and combo PHYs join Silvaco's Production-Ready Offerings.
MIPI C-PHY/D-PHY Combo
| Foundry | Product Name | Features | Part Number | Grade |
|---|---|---|---|---|
| TSMC | C-PHY/D-PHY ECM Universal in TSMC N2P | Supports MIPI C-PHY and MIPI D-PHY, 1T/1L, 3.0Gsps/3.0Gbps | ||
| TSMC | C-PHY/D-PHY Combo DSI TX+ in TSMC N5 | Supports MIPI C-PHY and MIPI D-PHY, 3T/4L, 4.5Gsps/4.5Gbps, full-speed internal loopback testability | ||
| TSMC | C-PHY/D-PHY Combo CSI RX+ in TSMC N5 | Supports MIPI C-PHY and MIPI D-PHY, 3T/4L, 4.5Gsps/4.5Gbps, full-speed internal loopback testability | ||
| TSMC | C-PHY/D-PHY Combo CSI-2 RX+ in TSMC N6 | Supports MIPI C-PHY and MIPI D-PHY, 3T/4L, 6.0Gsps/4.5Gbps, full-speed internal loopback testability | ||
| TSMC | C-PHY/D-PHY combo CSI-2 RX in TSMC N7 | Supports MIPI C-PHY and MIPI D-PHY, 3T/4L, 4.5Gsps/4.5Gbps | ||
| TSMC | C-PHY/D-PHY Combo CSI-2 TX+ in TSMC 16FFC | Supports MIPI C-PHY and MIPI D-PHY, 3T/4L, 4.5Gsps/4.5Gbps, full-speed internal loopback testability | ||
| TSMC | C-PHY/D-PHY Combo DSI RX+ in TSMC 16FFC | Supports MIPI C-PHY and MIPI D-PHY, 3T/4L, 4.5Gsps/6.5Gbps, full-speed internal loopback testability | ||
| TSMC | C-PHY/D-PHY Combo Universal in TSMC 16FFC | Supports MIPI C-PHY and MIPI D-PHY, 3T/4L, 8.0Gsps/6.5Gbps, full-speed internal loopback testability | ||
| TSMC | C-PHY/D-PHY Combo CSI-2 RX+ in TSMC 16FFC | Supports MIPI C-PHY and MIPI D-PHY, 1T/1L, 1.5Gsps/1.5Gbps | ||
| TSMC | C-PHY/D-PHY Combo DSI RX in TSMC 22ULP | Supports MIPI C-PHY and MIPI D-PHY, 3T/4L, 2.5Gsps/2.5Gbps | ||
| TSMC | C-PHY/D-PHY Combo CSI-2 TX in TSMC 22ULL | Supports MIPI C-PHY and MIPI D-PHY, 3T/4L, 2.5Gsps/2.5Gbps | ||
| TSMC | C-PHY/D-PHY Combo Universal in TSMC 22ULP | Supports MIPI C-PHY and MIPI D-PHY, 3T/4L, 4.5Gsps/4.5Gbps | ||
| TSMC | C-PHY/D-PHY Combo CSI-2 TX in TSMC 28HPC+ | Supports MIPI C-PHY and MIPI D-PHY, 3T/4L, 4.5Gsps/4.5Gbps | ||
| ST | C-PHY/D-PHY Combo CSI-2 TX+ in ST 28FDSOI | Supports MIPI C-PHY and MIPI D-PHY, 3T/4L, 3.5Gsps/2.5Gbps, full-speed internal loopback testability | ||
| ST | C-PHY/D-PHY Combo CSI-2 TX+ in ST 40LP | Supports MIPI C-PHY and MIPI D-PHY, 3T/4L, 3.5Gsps/2.5Gbps, full-speed internal loopback testability | C, I | |
| ST | C-PHY/D-PHY Combo CSI-2 TX+ in ST 40LP | Supports MIPI C-PHY and MIPI D-PHY, 2T/2L, 3.5Gsps/2.5Gbps, full-speed internal loopback testability | ||
| TSMC | C-PHY/D-PHY Combo CSI-2 TX in TSMC 40ULP | Supports MIPI C-PHY and MIPI D-PHY, 2T/2L, 1.5Gsps/1.5Gbps | ||
| TSMC | C-PHY/D-PHY Combo CSI-2 TX+ in TSMC 40ULP | Supports MIPI C-PHY and MIPI D-PHY, 1T/1L, 2.5Gsps/2.5Gbps, full-speed internal loopback testability | ||
| TSMC | C-PHY/D-PHY Combo CSI-2 TX+ in TSMC 40ULP | Supports MIPI C-PHY and MIPI D-PHY, 2T/2L, 2.5Gsps/2.5Gbps, full-speed internal loopback testability | 20X352 | C, I |
| TSMC | C-PHY/D-PHY Combo CSI-2 TX+ in TSMC 65LP | Supports MIPI C-PHY and MIPI D-PHY, 1L/1T, 1.5Gsps/1.5Gbps, full-speed internal loopback testability |
MIPI D-PHY
| Foundry | Product Name | Features | Part Number | Grade |
|---|---|---|---|---|
| TSMC | D-PHY DSI TX in TSMC N7 | Supports MIPI D-PHY, 4L, 4.5Gbps | ||
| GlobalFoundries | Supports MIPI D-PHY, 4L, 1.25Gbp | Supports MIPI D-PHY, 4L, 1.25Gbps | ||
| TSMC | D-PHY CSI-2 RX in TSMC 16FFC | Supports MIPI D-PHY, 4L, 1.25Gbps | ||
| GlobalFoundries | D-PHY CSI-2 TX in GF 22FDX | Supports MIPI D-PHY, 2L, 2.5Gbps | ||
| GlobalFoundries | D-PHY CSI-2 RX in GF 22FDX | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| GlobalFoundries | D-PHY CSI-2 RX in GF 22FDX | Supports MIPI D-PHY, 2L, 2.5Gbps | 20X271 | C, I |
| GlobalFoundries | D-PHY CSI-2 TX in GF 22FDX | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| GlobalFoundries | D-PHY DSI RX in GF 22FDX | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| GlobalFoundries | D-PHY DSI TX+ in GF 22FDX+ | Supports MIPI D-PHY, 2L, 2.5Gbps, full-speed internal loopback testability | ||
| GlobalFoundries | D-PHY CSI-2 RX in GF 22FDX+ | Supports MIPI D-PHY, 2L, 2.5Gbps | ||
| GlobalFoundries | D-PHY DSI-2 RX in GF 22FDX+ | Supports MIPI D-PHY, 2L, 2.5Gbps | ||
| TSMC | D-PHY CSI-2 TX in TSMC 22ULL | Supports MIPI D-PHY, 1L, 1.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY CSI-2 TX+ in TSMC 22ULL | Supports MIPI D-PHY, 4L, 2.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY Universal in TSMC 22ULL | Supports MIPI D-PHY, 4L, 2.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY Universal in TSMC 22ULP | Supports MIPI D-PHY, 4L, 2.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY Universal in TSMC 22ULP | Supports MIPI D-PHY, 2L, 2.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY Universal in TSMC 22ULP | Supports MIPI D-PHY, 2L, 2.5Gbps, full-speed internal loopback testability | ||
| UMC | D-PHY DSI RX in UMC 22ULP/22ULL | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| Samsung | D-PHY DSI TX+ in Samsung 28FDSOI | Supports MIPI D-PHY, 4L, 1.5Gbps, full-speed internal loopback testability | ||
| Samsung | D-PHY CSI-2 RX in Samsung 28FDSOI | Supports MIPI D-PHY, 2L, 1.5Gbps | ||
| TSMC | D-PHY CSI-2 TX+ in TSMC 28HPC+ | Supports MIPI D-PHY, 4L, 2.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY Universal in TSMC 28HPC+ | Supports MIPI D-PHY, 4L, 2.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY CSI-2 RX+ in TSMC 28HPC+ | Supports MIPI D-PHY, 2L, 1.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY DSI TX in TSMC 28HPC+ | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| TSMC | D-PHY CSI-2 RX in TSMC 28HPC+ | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| TSMC | D-PHY CSI-2 TX in TSMC 28HPC+ | Supports MIPI D-PHY, 2L, 2.5Gbps | ||
| TSMC | D-PHY Universal in TSMC 28HPC+ | Supports MIPI D-PHY, 4L, 2.5Gbps, full-speed internal loopback testability | ||
| SMIC | D-PHY CSI-2 TX+ in SMIC 28HPC+ | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| TSMC | D-PHY Universal in TSMC 40LP | Supports MIPI D-PHY, 1L, 1.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY CSI-2 TX in TSMC 40LP | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| TSMC | D-PHY CSI-2 TX+ in TSMC 40ULP | Supports MIPI D-PHY, 1L, 1.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY CSI-2 TX+ in TSMC 40ULP | Supports MIPI D-PHY, 4L, 1.5Gbps, full-speed internal loopback testability | ||
| SMIC | D-PHY CSI-2 TX+ in SMIC 28HPC+ | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| TSMC | D-PHY DSI TX in TSMC 55ULP | Supports MIPI D-PHY, 2L, 1.0Gbps | ||
| TSMC | D-PHY Universal in TSMC 65GP | Supports MIPI D-PHY, 4L, 2.5Gbps, full-speed internal loopback testability | ||
| Tower | D-PHY CSI-2 TX in Tower 65ISC | Supports MIPI D-PHY, 4L, 1.2Gbps | ||
| Tower | D-PHY CSI-2 TX in Tower 65ISC | Supports MIPI D-PHY, 2L, 1.2Gbps | ||
| TSMC | D-PHY CSI-2 TX in TSMC 65LP | Supports MIPI D-PHY, 2L, 2.5Gbs | ||
| TSMC | D-PHY CSI-2 TX in TSMC 65LP | Supports MIPI D-PHY, 4L, 1.5Gbs | ||
| TSMC | D-PHY CSI-2 TX in TSMC 90LP | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| TSMC | D-PHY CSI-2 TX+ in TSMC 90LP (90N65CIS) | Supports MIPI D-PHY, 4L, 2.5Gbps |
MIPI C-PHY
| Foundry | Product Name | Features | Part Number | Grade |
|---|---|---|---|---|
| TSMC | C-PHY DSI TX in TSMC 22ULL | Supports MIPI C-PHY, 3T, 2.5Gsps | ||
| TSMC | C-PHY DSI RX in TSMC 22ULL | Supports MIPI C-PHY, 3T, 2.5Gsps | ||
| TSMC | C-PHY CSI-2 TX+ in TSMC 40ULP | Supports MIPI C-PHY, 1T, 2.5Gsps, full-speed internal loopback testability |
MIPI M-PHY
| Foundry | Product Name | Features | Part Number | Grade |
|---|---|---|---|---|
| TSMC | M-PHY HS-G4 (11.66Gbps) in TSMC 40G | Supports MIPI M-PHY, 11.66Gbps |
LVDS/MIPI D-PHY Combo
| Foundry | Product Name | Features | Part Number | Grade |
|---|---|---|---|---|
| GlobalFoundries | LVDS/D-PHY DSI TX+ combo in GF 22FDX+ | Supports MIPI D-PHY and LVDS, 4CH/4L, 1039.5Mbps/2.5Gbps, full-speed internal loopback testability | ||
| TSMC | LVDS/D-PHY CSI-2 RX Combo in TSMC 28HPC+ | Supports MIPI D-PHY and LVDS, 4CH/4L, 600Mbps/1.5Gbps | ||
| Tower | LVDS/D-PHY CSI-2 TX Combo in Tower 65BSB | Supports MIPI D-PHY and LVDS, 3CH/2L, 600Mbps/1.2Gbps |
MIPI LVDS
| Foundry | Product Name | Features | Part Number | Grade |
|---|---|---|---|---|
| UMC | LVDS TX+ in UMC 40ULP | Supports LVDS, 4CH, 770Mbps, full speed loopback description | ||
| TSMC | LVDS TX in TSMC 40LP | Supports LVDS, 4CH, 1000Mbps | ||
| TSMC | LVDS RX in TSMC 40LP | Supports LVDS, 4CH, 1000Mbps | 20X331 | C, I |
ASA Motion Link
| Foundry | Product Name | Features | Part Number | Grade |
|---|---|---|---|---|
| TSMC | ASA Motion Link | ASA Motion Link v2.1 at up to 8.0 Gbps per lane |
Grade: C Commercial, I Industrial, A Automotive.
Ask about your process
Tell an IP specialist which foundry, node and link you’re working with. You’ll find out
which Mixel MIPI part fits and whether it’s already proven there.
Questions about MIPI IP
What mixed-signal IP does Silvaco offer?
Silvaco provides the complete Mixel mixed-signal interface IP product line: MIPI D-PHY, C-PHY and M-PHY, C-PHY/D-PHY and LVDS/D-PHY combo PHYs, LVDS, and ASA Motion Link. Mixel IP is silicon-proven on 13 nodes at 9 foundries.
What is the difference between D-PHY, C-PHY and M-PHY?
D-PHY sends data on up to four lanes with a forwarded clock lane. C-PHY embeds the clock in three-wire trios and carries 2.28 bits per symbol, so it reaches high throughput at a lower symbol rate. Both carry CSI-2 camera and DSI display traffic. M-PHY is a serial PHY with an embedded clock and multiple speed gears, used for UFS storage and UniPro chip-to-chip links. Mixel IP supports up to D-PHY v3.6 and C-PHY v2.1, backward compatible with earlier versions, at up to 6.5 Gbps per lane and 8.0 Gsps per trio, and M-PHY v4.1 up to HS-G4 (11.66 Gbps).
What is a C-PHY/D-PHY combo, and when is it used?
One PHY that supports both C-PHY and D-PHY on shared pins, so a single design can connect to C-PHY or D-PHY sensors and displays. The Mixel combo reuses D-PHY circuitry to save area and leakage. Most customers choose the Mixel combo over standalone C-PHY.
What are LVDS and the LVDS/D-PHY combo used for?
LVDS is a differential interface used for display and camera links outside MIPI, for example in industrial and automotive displays. The LVDS/D-PHY combo supports both on one PHY, so the same chip can drive LVDS or MIPI D-PHY displays.
What is ASA Motion Link?
ASA Motion Link is the Automotive SerDes Alliance standard for high-speed in-vehicle links, such as cameras and displays. Mixel ASA Motion Link IP supports v2.1 at up to 8.0 Gbps per lane (NRZ, speed grade 3).
Which foundries and nodes are available, and which are PRO IP?
Mixel IP is silicon-proven on 13 nodes at 9 foundries. The product tables on this page list what is readily available now as PRO IP, by foundry and node. If you don't see your process, talk to the IP team.
What does PRO IP mean?
PRO IP stands for Production-Ready Offerings: Silvaco IP characterized for specific foundry processes and available to license now. It is listed in the PRO IP Product Selection Guide and in the product tables on this page.
What deliverables and licensing come with Mixel IP?
A Mixel IP license includes a data sheet and specifications, integration guidelines, GDSII database, LEF file, LVS netlist, timing model, Verilog model, IBIS model, RTL, test benches, and customer support through production. Functional safety deliverables such as the DFMEA, FMEDA, and safety manual for automotive designs are also available. Talk to the IP team about licensing terms.
Is Mixel IP silicon-proven and ready for automotive use?
Mixel IP is silicon-proven on 13 nodes at 9 foundries, and Mixel was the first IP provider to demonstrate silicon-proven MIPI D-PHY, MIPI C-PHY and MIPI M-PHY. For automotive designs, Mixel IP is ASIL-B ready, developed under an ISO 26262 process certified up to ASIL-D since 2021, and available as automotive-grade IP supporting AEC-Q100 automotive Grade 1 and 2 designs.
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