Design IP

Design IP: Production-Ready Offerings for Production-Ready SoCs

Production-Ready Offerings (PRO IP) for SoC designs, characterized for specific foundry processes and available to license now: Mixel mixed-signal interface IP, standard cell libraries, memory compilers, AMBA, I3C and automotive networking IP

Browse PRO IP
Download the PRO IP catalog

Why license PRO IP

Most of a chip is built on standards: interfaces like MIPI, I3C and AMBA, and
building blocks like standard cells and memory compilers. Designing them in-house takes
design, verification and foundry characterization but rarely sets a chip apart. PRO
IP lets your team spend that effort where it does.

Time to market

PRO IP is characterized for specific foundry processes and delivered with the views your flow needs, so integration starts right away instead of after a block development cycle.

Lower risk

PRO IP is production-ready on the processes listed below, and the Mixel product line is silicon-proven on 13 nodes at 9 foundries. Support continues from integration through production.

Focus where it matters

Owning a block in-house means engineering, verification, foundry characterization and support for every process variant, long after tape-out. Developing and maintaining IP across processes is what we do, so your team doesn’t have to.

Find the IP for your design

PRO IP covers interface, foundation and system IP. Coverage by foundry and node differs by product line, and the table below lists it for each one.

Mixel interface IP

Mixel’s first MIPI PHYs date to 1998, and the company has held a MIPI Alliance seat since 2006. It joined Silvaco in August 2025 and still ships under its own name.

Mixel interface IP

Silvaco’s Mixel product line covers MIPI D-PHY, C-PHY and M-PHY, C-PHY/D-PHY and LVDS/D-PHY combos, LVDS, and ASA Motion Link. Mixel IP is silicon-proven on 13 nodes at 9 foundries, and Mixel was the first IP provider to demonstrate silicon-proven MIPI D-PHY, C-PHY and M-PHY. Mixel was founded in 1998 and joined the MIPI Alliance in 2006.
Explore Mixel IP

Foundation and system IP

Libraries and compilers characterized per foundry process, plus synthesizable cores for the logic that ties them together.

Foundation IP

Pick the track height and Vt mix your design needs instead of settling for one fixed library. The standard cell range covers 28 to 180 nm; SRAM, ROM and register-file compilers cover 22 to 130 nm, all enabled at TSMC, GlobalFoundries and UMC. Low Power Foundation IP, GPIO and LVDS I/O complete the line.
Standard Cell
Memory Compilers
Interface IP
Low Power Foundation IP

Foundation LVDS I/O is transmitter and receiver cells at the pad, for the I/O ring. The Mixel LVDS PHY is a separate product for display links.

AMBA IP cores and subsystems

AXI, AHB and APB controllers, plus the bus fabrics and bridges that join them. The pre-integrated subsystems include a secure one built for IoT. Synthesizable, so no node lock-in.
See AMBA IP

Automotive networking IP

FlexCAN, MultiCAN, LINFlex and FlexRay controllers for ASIL-B functions such as steer-by-wire and brake-by-wire.

Mixel automotive PHYs: ASIL-B D-PHY, ASA Motion Link.

See Automotive IP

I3C interface

I3C cores for sensor buses that need speed on few pins. They support in-band interrupts, run at low power and keep your existing I2C devices on the same bus.
See I3C IP

Embedded processors

The M8051EW for low-power 8-bit control, and ColdFire V1, V2 and V4 at 32 bits, as cores or full processor platforms.

See Embedded Processors

Power management

Two LDO regulators, rated 30 mA and 250 mA, with outputs adjustable from 0.45 to 0.9 V. A 0.45 V bandgap reference completes the set. All three run on TSMC N3P.

See Power Management IP

Other IP

An IEEE 1149.7 TAP controller: JTAG debug over two pins, with shorter scan times.

See Other IP

IP management

Software that tracks the IP you license, the IP you build, and where each one ends up.

IP Grid

IPVault is where your IP lives: cataloged, stored and handed out, with support tickets and license records alongside. IPAudit tells you which IP sits inside a given SoC design.

See I3C IP

Xena IP Management

One record for the business and engineering sides of your IP. Xena keeps an enterprise catalog, locks release versions and ties access to license terms.

See VarMan XMA

Check your foundry and node

AMBA, I3C and the automotive networking controllers are soft IP, synthesized onto whatever node you choose. Hard IP is
characterized per process, which makes your foundry and node the first filter.

PRODUCT LINE FOUNDRIES PROCESS NODES
MIPI C-PHY/D-PHY combo Mixed PHY IP TSMC, STMicroelectronics TSMC N2P down to 65 nm, including N5, N6, N7 and 16FFC
MIPI D-PHY Mixed PHY IP TSMC, GlobalFoundries, Samsung, UMC, Tower 7 to 90 nm, from TSMC N7 to TSMC 90LP, including GlobalFoundries 22FDX
MIPI C-PHY Mixed PHY IP TSMC 22 and 40 nm
MIPI M-PHY Mixed PHY IP TSMC 40 nm
LVDS/D-PHY combo Mixed PHY IP GlobalFoundries, TSMC, Tower 22 to 65 nm
LVDS Mixed PHY IP TSMC, UMC 40 nm
Standard cell libraries Foundation IP TSMC, GlobalFoundries, UMC 28 to 180 nm
Memory compilers Foundation IP TSMC, GlobalFoundries, UMC 22 to 130 nm
Power management System IP TSMC N3P

Node not listed? Ask the IP team. Memory compilers can be characterized to custom PVT corners on request.

What you can check before you sign

IP buyers look at silicon history and deliverables before they look at price.

9 foundries, 12 nodes

with working Mixel PHY silicon

1 billion+

units shipped with Silvaco automotive networking controllers

ISO 11898-1 · ISO 26262

CAN to ISO 11898-1, ASIL-B ready, Proven-in-Use under ISO 26262 Part 8

Liberty · LEF · GDSII

views in every PRO IP delivery, as fully characterized, DRC/LVS-clean instances

ISO 9001

certified quality management at Silvaco

Customer · Mixel MIPI PHY IP

November 2025

indie

indie designs radar front-end modules and MMICs for automotive safety systems. Its radar processors run Mixel's ASIL-B MIPI D-PHY CSI-2 transmitter and receiver, delivered with a safety manual and certified safety documentation for AEC-Q100 Grade 1 designs.

“We needed a MIPI IP provider that could support our strict automotive requirements to further our radar portfolio and enable efficient and scalable ADAS architecture solutions. Through our long-standing partnership with Mixel and their extensive automotive experience, we had full confidence in Mixel’s capabilities and reliability.”

Peter Gulden, EVP Radar Systems and Software, indie

Customer

SURGE 2025

Silicon Creations

“As an IP provider, the ability to efficiently port designs to the latest advanced processes and adapt to changing process requirements is essential.”

Randy Caplan, CEO and Co-founder, Silicon Creations

Catalog · PDF

Summer 2026

PRO IP product selection guide

Every PRO IP part number with its foundry and node, from MIPI PHYs to soft IP, and applications by market.

Press release

March 2026

Mixel MIPI PHY IP joins PRO IP

D-PHY v3.5, C-PHY v2.1, M-PHY v4.1, the combo PHYs and ASA Motion Link SerDes, plus a D-PHY RX+ that needs 35% less area and 50% less leakage than a full Universal configuration.

Press release

March 2026

C-PHY/D-PHY combo IP on TSMC N2P

MIPI D-PHY v3.6 with embedded clock mode, on TSMC's N2P process. Mixel MIPI PHY IP now has silicon on ten TSMC nodes.

Bring your foundry, your node and
your block list

Tell the IP team what you’re building and where. You’ll hear which blocks already have
silicon on that process and how licensing works.

Request a technical briefing
Download the PRO IP catalog

Questions about semiconductor IP cores

What is semiconductor IP?

Semiconductor IP is a design block, already built and verified, that you license for your own SoC instead of building it in-house. Typical examples are a MIPI PHY, an SRAM compiler, a standard cell library and an AMBA bus controller. Licensing proven IP cores frees your engineers for the logic that sets your product apart.

Foundation IP forms the chip's physical base: standard cells, memory compilers and general-purpose I/O, each characterized for one foundry process. Interface IP carries data on and off the die. Silvaco's interface IP is Mixel's MIPI PHYs and SerDes, plus the I3C cores. LVDS I/O sits in both groups.

Coverage depends on the product line. For Mixel PHY IP, the silicon record runs to nine foundries and twelve nodes, with the C-PHY/D-PHY combo now on TSMC N2P. Foundation IP runs on TSMC, GlobalFoundries and UMC processes: 28 to 180 nm for standard cells, 22 to 130 nm for memory compilers. Soft IP is synthesizable.

You get fully characterized instances, clean on DRC and LVS and delivered in Liberty, LEF and GDSII for your flow. Memory compilers build each instance to your configuration, and custom PVT characterization is available on request. Automotive programs also get functional safety documentation and a safety manual from Mixel, as indie did.

Yes. Nothing enters the PRO IP range without a production silicon record across several foundries. The automotive networking controllers go further: over a billion units shipped, and Proven-in-Use status under ISO 26262 Part 8. Mixel's radar customer indie runs its MIPI PHY in AEC-Q100 Grade 1 designs.

Production Ready Offerings, or PRO IP, is Silvaco’s name for IP with a silicon track record and full characterization, ready to license today. It covers Mixel MIPI PHYs, standard cell libraries, memory compilers, AMBA and I3C cores, and the automotive networking controllers. The PRO IP product selection guide lists every part number.

Related

All of AI-Driven Design

MIPI IP

Mixel D-PHY, C-PHY and M-PHY physical layer IP

Foundation IP

Standard cells, memory compilers and I/O

AMBA

Bus controllers, fabrics and subsystems

AMBA

Automotive IP

I3C

Sensor connectivity cores

Embedded Processors

ColdFire and 8051 cores

Power Management

LDO regulators and a bandgap reference on TSMC N3P

IP Grid

IPVault and IPAudit

Xena IP Management

Catalog, releases and license-based access

Automotive Semiconductor

Silvaco for automotive chips