A

Advanced packaging

Advanced packaging combines two or more dies in a single package. They sit side by side on an interposer or stack vertically, joined by through-silicon vias, microbumps or hybrid bonds. Split a design across dies and the joints become your problem. Heat, mechanical stress and signal integrity at each one are design decisions now, not assembly.

Covered on Advanced Packaging

Related terms

Parasitic extraction\nTCAD simulation Parasitic extraction\nTCAD simulations

AMBA

AMBA, Arm's Advanced Microcontroller Bus Architecture, is an open bus standard for tying processors, memory and peripherals together on chip. AXI carries high-bandwidth traffic, AHB runs system buses and APB serves slow peripherals. Silvaco licenses AMBA cores and complete subsystems. Your blocks then connect over a bus every SoC team already knows.

Covered on AMBA

Related terms

I3C\nInterface IP\nSemiconductor IP

Atomistic device simulation

Atomistic device simulation treats a device as individual atoms on a crystal lattice, not as a smooth continuum. Band structure, quantum confinement and strain come out of the atomic arrangement itself instead of from averaged material values. You need that for a new material, or a channel a few nanometers wide, where a continuum model has no fitted parameters yet.

Covered on Victory Atomistic

Related terms

TCAD simulation

C

Computational lithography

Computational lithography uses simulation to work out how a mask pattern will actually print, then alters the mask until the wafer shows what the designer drew. Process proximity Compensation does most of that work. Exposure, resist and etch each warp a feature, so the software moves mask edges to compensate and re-simulates before you commit to a mask.

Covered on Lithography

Related terms

Plasma simulation\nProcess proximity Compensation

CSI-2 and DSI

CSI-2 and DSI are the two MIPI protocols for image traffic. The Camera Serial Interface (CSI-2) brings pixels in from an image sensor. The Display Serial Interface (DSI) sends them out to a panel. Either one rides on a D-PHY or C-PHY physical layer, so a part called a CSI-2 receiver tells you its job by name.

Covered on MIPI

Related terms

MIPI\nMIPI C-PHY\nMIPI D-PHY

D

Digital twin

A digital twin, in fab terms, is a model of a real process trained on simulation output and measured wafer data. Change an implant dose or an anneal time and it predicts the effect on structure, device behavior and yield. You get the answer a split lot would give. The wafer moves only once the change looks right.

Covered on FTCO

Related terms

Fab Technology Co-Optimization (FTCO)\nSurrogate model

E

EDA software

EDA software (electronic design automation) covers the tools that carry your integrated circuit from schematic to tape-out. Simulating the circuit, drawing the layout, extracting its parasitics and checking it against foundry rules are all EDA work. Silvaco builds tools for each step. Its TCAD simulation works a level below that, on the process and the device.

Covered on Products & Workflows

Related terms

Parasitic extraction\nPhysical verification\nSPICE simulation\nTCAD simulation

F

Fab Technology Co-Optimization (FTCO)

Fab Technology Co-Optimization (FTCO) gives fab and process engineers TCAD-grade answers without a TCAD specialist in the loop. FTCO trains a non-linear model on physics simulation and your own measured data until it tracks the process closely enough to serve as its digital twin. Then you ask it questions in real time.

Covered on FTCO

Related terms

Digital twin\nSurrogate model\nTCAD simulation

FastSPICE

FastSPICE trades a little accuracy for a lot of capacity in circuit simulation. It splits the circuit into partitions, solves busy ones often and quiet ones rarely, and passes changes between them as events. That's how you simulate a full memory array or display panel at all. SmartSpice Pro is the FastSPICE engine in Silvaco's circuit simulation line.

Covered on SmartSpice Pro

Related terms

SPICE simulation

Foundation IP

Foundation IP, sometimes called physical IP, covers the pre-built blocks you assemble a chip from. Logic comes from standard cells, on-chip memory from memory compilers, and the pads from I/O cells. Silvaco's foundation IP spans standard cells, memory compilers, interface IP and low-power foundation IP. Each is delivered for a named foundry process.

Covered on Foundation IP

Related terms

Interface IP\nMemory compiler\nSRAM compiler\nStandard cell library

H

High-sigma analysis

High-sigma analysis confirms a circuit still meets spec at failure rates of 4 to 6 sigma or rarer. Any cell copied millions of times on one die needs it. A memory bit-cell may have to clear 7 sigma, which plain Monte Carlo could take billions of runs to show. VarMan gets there with a limited number of simulations.

Covered on VarMan

Related terms

SPICE simulation\nVariation-aware design

I

I3C

I3C, from the MIPI Alliance, is a two-wire sensor bus built to bring I2C and SPI links together on one interface. Dynamic addressing, in-band interrupts and faster data modes come on top. Silvaco's I3C IP is built to I3C v1.1, I3C Basic included. The IP handles SDR, DDR and HDR-BT transfers behind an APB host interface.

Covered on I3C

Related terms

AMBA\nInterface IP\nMIPI

Interface IP

Interface IP is licensed circuitry that moves signals in and out of a chip. Closest to the package are I/O cells: Silvaco has general-purpose I/O and 2 Gbps LVDS I/O, both with ESD protection. Above them sit physical layers such as Mixel's MIPI D-PHY, and on-chip bus controllers like AMBA and I3C that your logic talks to.

Covered on Interface IP

Related terms

AMBA\nI3C\nLVDS\nMIPI

IR drop analysis

IR drop analysis measures how much supply voltage a chip's power network loses to its own resistance before current reaches each transistor. Trace that loss from the package pins down to every device and you find the spots where the voltage falls low enough to slow the circuit, or break it. InVar runs it alongside power and electromigration checks.

Covered on InVar

Related terms

Parasitic extraction\nSPICE simulation

ISO 26262

ISO 26262 sets the functional safety requirements for electrical and electronic systems in road vehicles. Each safety goal gets an Automotive Safety Integrity Level, from ASIL A, the lowest, up to ASIL D. If you put licensed IP in a safety function, you need evidence behind it: a Part 8 proven-in-use record, or certified development with a safety manual.

Covered on Automotive Semiconductor

Related terms

Semiconductor IP

L

LVDS

LVDS, low-voltage differential signaling, sends each bit as a small voltage difference across a pair of wires. That keeps power and electromagnetic interference low at high data rates. TIA/EIA-644 defines the standard. From Mixel you can license an LVDS serializer, a matching deserializer, and D-PHY/LVDS combo parts.

Covered on LVDS

Related terms

Interface IP\nMIPI D-PHY

M

Memory compiler

A memory compiler is a generator for on-chip memory. You set the word count, bits per word, column mux and power options, and it builds that exact instance with its layout and model set. Nobody draws the array by hand. Silvaco's memory compilers cover single- and dual-port SRAM, 1- and 2-port register files, and ROM.

Covered on Memory Compilers

Related terms

Foundation IP\nSRAM compiler

MIPI

MIPI is a set of interface specifications from the MIPI Alliance, written for the short, high-speed connections inside a phone, a car or any device with a camera and a screen. Each protocol rides on a physical layer, or PHY, that you license. Mixel, part of Silvaco, has designed MIPI PHYs since 1998 and supplies D-PHY, C-PHY and M-PHY.

Covered on MIPI

Related terms

CSI-2 and DSI\nI3C\nMIPI C-PHY\nMIPI D-PHY\nMIPI M-PHY\nSemiconductor IP

MIPI C-PHY

MIPI C-PHY is a MIPI physical layer that sends image data as 3-phase symbols over three-wire groups called trios. The clock is embedded in the symbol transitions. That leaves you no separate clock lane to route. Silvaco's C-PHY IP comes from Mixel and carries CSI-2 and DSI traffic, on its own or in a C-PHY/D-PHY combo.

Covered on MIPI C-PHY

Related terms

CSI-2 and DSI\nMIPI\nMIPI D-PHY

MIPI D-PHY

MIPI D-PHY is the physical layer beneath CSI-2 camera links and DSI display links. It uses a clock lane plus one or more data lanes, and idles in a low-power state between high-speed bursts. You can license Mixel's D-PHY IP as a transmitter or receiver, or as TX+ and RX+ versions built for production test.

Covered on MIPI D-PHY

Related terms

CSI-2 and DSI\nLVDS\nMIPI\nMIPI C-PHY

MIPI M-PHY

MIPI M-PHY is MIPI's serial physical layer for power-sensitive links, such as a phone's connection to its UFS flash storage or a link between two chips. Data runs in high-speed (HS) gears. Slower PWM gears carry low-speed signaling, and the link hibernates between bursts so you pay for power only while data moves. The M-PHY IP Silvaco licenses is Mixel-designed.

Covered on MIPI M-PHY

Related terms

MIPI\nMIPI D-PHY

P

Parasitic extraction

Parasitic extraction works out the unwanted resistance and capacitance a layout adds, from every wire, via and contact. The result is a netlist that captures what the manufactured chip will behave like, rather than how the schematic promised it would. For full-chip extraction, Silvaco's tool is HiPer.

Covered on HiPer

Related terms

EDA software\nIR drop analysis\nParasitic reduction

Parasitic reduction

Parasitic reduction, or RC reduction, cuts an extracted netlist down to a fraction of its resistors, capacitors and inductors while holding its electrical behavior inside an error budget you set. Post-layout simulation then runs on a much smaller netlist and gives the same answer. Jivaro Pro does the reduction with patented mathematical approaches.

Covered on Jivaro Pro

Related terms

Parasitic extraction\nSPICE simulation

Photonic simulation

Photonic simulation predicts where light goes in a device by solving Maxwell's equations through its real geometry. Ray tracing won't do, because integrated photonic structures are only a few wavelengths across. You have to solve for the electromagnetic field everywhere in the structure. Full-wave methods such as FDTD do that. X-PIC Pro Photonics is the Silvaco product for this work.

Covered on Photonics

Related terms

TCAD simulation

Physical verification

Physical verification is the last set of checks on an IC layout before tape-out. Design rule checking (DRC) tests every shape against the foundry's width, spacing and overlap rules. Layout versus schematic (LVS) confirms the drawn connections match your circuit, with no shorts, opens or floating nets. SmartDRC/LVS runs both checks in Silvaco's flow.

Covered on SmartDRC/LVS

Related terms

EDA software\nProcess design kit (PDK)

Plasma simulation

Plasma simulation models the plasma inside an etch or deposition chamber at individual particles, not as one gas with an averaged temperature. A particle-in-cell method pushes ions, electrons and neutrals through the fields they create and tracks how they collide. You get the energy and angle of ions arriving at the wafer, which an averaged model misses.

Covered on Plasma

Related terms

Computational lithography\nTCAD simulation

Process design kit (PDK)

A foundry's process design kit (PDK) bundles what designers need for one process: transistor models, design rules, DRC and LVS decks, and layout cells. Your tools read it, which is how the layout you draw stays manufacturable. Silvaco publishes a sample of the PDKs its tools support, with Arm, Tower Semiconductor and X-FAB among the foundries.

Covered on Process Design Kits

Related terms

Foundation IP\nPhysical verification\nSPICE model extraction

Process proximity Compensation

Process Proximity Compensation (PPC) adjusts a mask so features print in the shape they were drawn. Exposure, resist and etch all shift edges, most where features crowd together. Left alone, a line comes out short, thin or rounded at the corners. PPC models those shifts and biases your mask edges against them. Silvaco's PPC product is called Process Proximity Compensation.

Covered on Process Proximity Compensation

Related terms

Computational lithography

S

Semiconductor IP

Semiconductor IP is a pre-designed, verified circuit block licensed for use in someone else's chip. It ranges from foundation IP, such as standard cells and memory compilers, to interface IP, such as MIPI PHY or an AMBA bus controller. You license the blocks most chips share. Your team designs the part only your product has.

Covered on Design IP

Related terms

AMBA\nFoundation IP\nInterface IP\nMIPI

SPICE model extraction

SPICE model extraction turns measured or simulated device data into the parameters a circuit simulator needs. You start with current-voltage and capacitance curves, from a probe station or from TCAD. Then you fit a standard compact model (BSIM, HSPICE or PSP, for example), until it reproduces those curves. Silvaco does this in Utmost IV.

Covered on Utmost IV

Related terms

SPICE simulation\nTCAD simulation

SPICE simulation

SPICE simulation solves a circuit netlist for the voltage at every node and the current in every branch, using compact device models. You can solve for a DC operating point, sweep frequency, or step through time. Analog signal integrity all depends on it. Nothing more abstract will show you a PLL's jitter or the offset in a bandgap.

Covered on Circuit Simulation

Related terms

EDA software\nFastSPICE\nSPICE model extraction

SRAM compiler

An SRAM compiler is a memory compiler for static RAM. Enter the capacity, word width and column mux your block needs, and it returns a characterized, laid-out instance instead of a hand-drawn array. Silvaco's single- and dual-port SRAM compiler targets a named foundry process. You choose from the power modes that process offers.

Covered on SRAM Compiler

Related terms

Foundation IP\nMemory compiler\nSemiconductor IP

Standard cell library

A standard cell library is the set of logic cells, from inverters to flip-flops, that synthesis and place-and-route tools build your digital blocks from. Cells share a common height so they line up in placement rows, with timing and power data for a single process. Silvaco's libraries come as CORE, Power Management IP (PMI) and ECO sets, with multi-Vt options.

Covered on Standard Cell

Related terms

Foundation IP\nMemory compiler\nSemiconductor IP

Surrogate model

A surrogate model stands in for a slow physics simulation, trained on that simulation's own results. Give it a process setting and in real time it returns what the simulator would have: the structure, the device metrics, a full I-V curve. Its limits are its training data. Stay inside that range, or go back to the simulator.

Covered on Surrogate Modeling

Related terms

Digital twin\nFab Technology Co-Optimization (FTCO)\nTCAD simulation

T

TCAD simulation

TCAD simulation, short for technology computer-aided design, uses physics to model how a semiconductor device gets built and how it then performs. Process simulation steps through implantation, oxidation, etch and deposition to build a virtual structure. Device simulation solves carrier transport in it so you can predict current, capacitance, self-heating and breakdown voltage before any wafer exists.

Covered on TCAD

Related terms

Atomistic device simulation\nEDA software\nFab Technology Co-Optimization (FTCO)\nSPICE model extraction

V

Variation-aware design

Variation-aware design means proving a circuit meets spec across the spread of real silicon, not only at a handful of typical corners. FinFET and FD-SOI nodes pushed supply and threshold voltages lower. That widened the spread enough to make heavy Monte Carlo analysis routine. VarMan and VarMan XMA give you the same answer with far fewer simulations than brute force.

Covered on VarMan

Related terms

High-sigma analysis\nSPICE simulation