Other IP
Other IP: IEEE 1149.7 TAP controller for debug and test
Short on pins? Silvaco’s IEEE 1149.7 TAP controller runs your SoC’s test and debug over two of them. It connects straight to the IEEE 1149.1 test logic the chip already has.
JTAG IP down to two pins,
across every 1149.7 class
The controller covers all six classes IEEE 1149.7-2009 defines. You pick the options in hardware when you configure it, and the chip’s IEEE 1149.1 logic stays where it is.
Full feature set, from T0 up
You get every mandatory and optional feature, command and register in IEEE Std 1149.7-2009. At class T0 it stays strictly compliant with IEEE 1149.1, and still handles several 1149.1 TAPs on one chip.
Two pins for test and debug
From class T4, all signalling runs on TMSC and TCKC. TDI and TDO can come off the package or take other jobs, and test and debug both run through the pair that’s left. Need several controllers? Class T3 connects them in a 4-wire star.
Shorter scan paths
Class T2 lets a scan bypass the chip’s system test logic, cutting instruction and data register scans to a 1-bit path. Class T5 opens non-scan transfers on as many as two channels, with up to sixteen on-chip clients per channel.
Small, and guarded at the port
About 2,500 gates at class T4 in a typical 90 nm process. Full T5 data channels add roughly 1,300 more. Power-down support is optional, and a firewall cuts TCK to the on-chip test logic when a debugger is hot-connected.
Three reasons to put it on your chip
SoC debug and test access
Debuggers and test equipment come in through the same two-pin port.
JTAG-based production test
Keep your IEEE 1149.1 test flow and let the T2 bypass cut scan time.
Designs constrained on pin count
At class T4, TDI and TDO are free for something else.
What ships with part 70006
Part 70006 arrives as synthesizable Verilog source. The package also holds the integration testbench and its tests, the documentation, and scripts that run simulation and synthesis in common EDA tools. No form stands between you and the brief.
70006
Silvaco part number for the IEEE 1149.7 TAP controller
T0–T5
every IEEE 1149.7 class supported
2 pins
test and debug together, at class T4
~2,500 gates
at class T4, typical 90 nm process
Product brief · PDF
IEEE 1149.7 Compact TAP
The six classes, the interface signals, the options you can configure and the full deliverables list.
Size the port to your pin budget
Start from the pins you can spare. An IP specialist matches that, and the way your chip is tested and debugged now, to an IEEE 1149.7 class. Licensing, evaluation and availability for your foundry come up in that same conversation.
Before you license the IEEE 1149.7 TAP controller
What is a TAP controller?
It's the state machine behind every JTAG port. The TAP, or test access port, controller lets outside test and debug tools into the chip and shifts instructions and data through its test logic. Silvaco's IEEE 1149.7 TAP controller does the same job with two pins instead of the usual four or five.
What is IEEE 1149.7 and how does it differ from 1149.1?
IEEE 1149.1 was built to test board-level interconnect. IEEE 1149.7-2009 keeps that test access port and extends it for device programming, application debug, power management and chip integration. Those additions sit in six classes, T0 through T5. T0 is strictly 1149.1-compliant. Every class above it adds to the one beneath.
What is 2-pin access?
It's IEEE 1149.7 class T4 operation. Every signal travels on TMSC and TCKC, where IEEE 1149.1 uses four pins, or five with a reset. That frees TDI and TDO: drop them from the package or reassign them. One pin pair then carries test and debug traffic alike.
What other debug IP is available?
Silvaco's embedded processors carry their own debug hardware. The ColdFire V1 core debugs over a single-wire Background Debug Mode interface, with trace available as an option. On the M8051EW, an On-Chip Instrumentation unit handles breakpoints, single-step and trace over IEEE 1149.1 JTAG. Both sit on the Embedded Processors page.
Is the IP silicon proven?
Yes. It's production-proven debug IP. It ships as synthesizable Verilog, and before tape-out you can run it through the bundled integration testbench inside your own design flow. Ask an IP specialist for silicon references on a process close to yours.
What happened to Cello and Viola?
They aren't IP blocks. Cello and Viola are Silvaco software for building libraries. SilTerra has used them to optimize and characterize its standard cell and I/O libraries, and Cello also takes on FinFET standard cell layout. Looking for ready-made libraries instead? Start at Foundation IP.
Related
AMBA IP
Cores and subsystems for the AMBA on-chip bus
Embedded Processors
32-bit ColdFire and 8-bit 8051 cores, from 19K gates
Foundation IP
Standard cell and memory compiler libraries, low-power options included
All of Design IP
Every Silvaco IP family, MIPI PHYs included