Library Characterization & Optimization

FinFET and FDSOI Cell Library Development​

Auto Cell-layout Generation and Optimization

Complete Characterization and Analysis Solution​

Library Characterization & Optimization

FinFET and FDSOI Cell Library Development​

Auto Cell-layout Generation and Optimization

Complete Characterization and Analysis Solution​

Overview

The Silvaco Library Platform is the most comprehensive tool suite for efficient creation and validation of digital cell libraries.  It is engineered to support libraries containing thousands of cells.

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Cello Library Creation, Migration and Optimization

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Viola Cell Library Characterization and Variation Modeling

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SmartSpice Circuit Simulator

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Liberty Analyzer for Liberty Files

Library Creation, Migration and Optimization

Cello is the industry’s most versatile, integrated and easy-to-use solution for digital cell library creation, optimization and process migration. It enables designers of digital CMOS ICs to custom-tailor digital cell libraries and explore the impact of alternate device models, design rules and cell architectures.

Library Characterization

Viola is a unique, all-inclusive package for fast and accurate characterization of digital cell libraries. The package includes a powerful SPICE-based characterization engine with fully automated stimulus generation, a library model checker and a databook generator.

Liberty File Analysis

Liberty Analyzer displays, analyzes, compares and validates Liberty™ files for timing, power, noise and area. Liberty Analyzer handles multiple NLDM, NLPM, CCS and ECSM models at library, cell, pin and individual arc levels while providing insightful statistical data. It displays and plots relative and absolute differences with configurable thresholds for easy spotting of trends and outliers. Its validation routines include a sanity check that validates libraries for use with any design flow.

Resources

Standard Cell Layout Migration and Optimization


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Customers

Phillip Christie
 Silvaco’s library creation and validation process is extremely fast and flexible. This effectively allows us to conduct more experiments and to predict the resulting impact at higher design levels. For instance, we may change the transistor model to a high-performance FinFET device or change the cell architecture or the routing strategy. With cell creation and characterization integrated in one tool which makes extensive use of parallel computing resources, we can very quickly produce a new prototype library that will help us predict the system-level effects of the changes. 

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