Power Management IP
Power management IP: LDO regulators and voltage references
Silvaco power management IP gives your TSMC 3 nm N3P design two LDO regulators and a bandgap reference, so every block on the die can run from its own regulated supply.
What you can license, and on which process
Three blocks, one process: TSMC’s 3 nm N3P FinFET. Each ships with a SPICE netlist, GDSII, a behavioral model and a user’s guide.
LDO regulator, 250 mA
Up to 250 mA from a 1.2 V supply. You set the output from 0.45 to 0.9 V in 50 mV steps, and it stays stable without an output capacitor. Quiescent and sleep current are low, and a 1 A/ns load step moves the output less than 50 mV.
LDO regulator, 30 mA
The same output range for lighter loads, in 3,400 µm². Supply rejection climbs to 49 dB typical at 1 kHz. A speed or static-power trade-off option lets you pick which one matters.
Bandgap voltage reference
Feed it 1.0 V and you get a fixed 0.45 V reference. Its low temperature coefficient keeps drift under 5 mV from 0 to 100 °C. PSRR tops 40 dB at DC, and the whole block draws about 1 mW.
Looking for the Power Management Kit?
That’s a separate product, a set of power-gating and multi-voltage cells that ship with some Silvaco standard cell libraries. Silvaco’s LDOs and bandgap reference are analog hard IP. They make the supplies those cells switch.
Published specifications
Figures from each product’s datasheet. A dash means the parameter doesn’t apply.
| SPECIFICATION | LDO, 250 mA | LDO, 30 mA | BANDGAP REFERENCE |
|---|---|---|---|
| Process | TSMC 3 nm N3P FinFET | TSMC 3 nm N3P FinFET | TSMC 3 nm N3P FinFET |
| Supply voltage | 1.2 V (1.08–1.32 V) | 1.2 V (1.08–1.32 V) | 1.0 V ±10% |
| Output voltage | 0.45–0.9 V | 0.45–0.9 V | 0.45 V fixed |
| Output step | 50 mV | 50 mV | — |
| Maximum load current | 250 mA | 30 mA | — |
| PSRR, low frequency | 36 dB at < 1 kHz | 49 dB typ, 40 dB min at 1 kHz | > 40 dB at DC |
| PSRR, high frequency | 12 dB at > 10 MHz | 38 dB typ, 29 dB min at 10 MHz | |
| Load transient, 1 A/ns | < 50 mV | < 18 mV | — |
| Output variation, 0–100 °C | — | — | < 5 mV |
| Output capacitor | None | None | — |
| Power consumption | ~1 mW | ||
| Silicon area | 3,400 µm² | ||
| Operating temperature | −40 to 125 °C | −40 to 125 °C | −40 to 125 °C |
Figures from each product’s datasheet. A dash means the parameter doesn’t apply.
Where power management IP fits in your SoC
On-chip voltage regulation at advanced nodes
Regulate right at the block, on N3P, with no external capacitor to route out.
Always-on and sleep-mode domains
Low sleep current keeps an always-on supply up while the rest of the chip powers down.
Precision reference generation
A 0.45 V reference that moves less than 5 mV across 0 to 100 °C.
Mixed-signal SoC power
Give analog, RF and digital subsystems their own regulated supplies on one die.
Check the numbers before you commit
Every datasheet downloads without a form. Hold the figures against your power budget first.
TSMC N3P
3 nm FinFET process for all three blocks
250 mA · 30 mA
maximum load of the two regulators
50 mV
output steps between 0.45 and 0.9 V
−40 to 125 °C
functional temperature range, all three
Datasheet · PDF
LDO voltage regulator, 250 mA
Transient and PSRR figures for the 250 mA regulator, plus everything that ships with it.
Datasheet · PDF
LDO voltage regulator, 30 mA
PSRR limits and silicon area for the 30 mA regulator, with the same deliverables.
Datasheet · PDF
Bandgap voltage reference, 0.45 V
Adds OA schematics, LEF and an integration guide to the usual netlist, GDSII and behavioral model.
Plan your supplies with an IP specialist
Give an IP specialist your foundry, process node and the rails you need to regulate.
You’ll find out what’s available for your process and how licensing works. Ask, too,
for any figure a datasheet leaves out.
Power management IP questions
What is an LDO regulator?
A low-dropout (LDO) regulator is a linear regulator that holds its output steady just below its input. That gives one block of a chip a clean local supply. Silvaco's two LDOs run from 1.2 V and output 0.45 to 0.9 V, at up to 30 or 250 mA, with no external output capacitor.
What is a bandgap voltage reference?
A bandgap voltage reference produces a voltage that barely moves as temperature and supply change, so regulators, converters and other analog blocks can measure against it. At 0.45 V, Silvaco's version drifts less than 5 mV between 0 and 100 °C on a 1.0 V supply, with PSRR above 40 dB at DC.
Which process nodes are available?
All three blocks are implemented in TSMC's 3 nm N3P FinFET process, and that's the process each datasheet covers. Designing on a different foundry or node? Raise it with an IP specialist early, before your supply plan starts to depend on these blocks.
What quiescent current does the LDO draw?
Both LDOs are low-quiescent-current designs with low sleep current. The 30 mA regulator also has a speed or static-power option, so you can trade response for standby draw where it matters. For figures at your load and operating point, ask an IP specialist.
How does this differ from the Power Management Kit?
The Power Management Kit sits in Silvaco's standard cell offering, adding power-gating and multi-voltage cells to some of its standard cell libraries. Silvaco power management IP is analog hard IP. Its LDO regulators and bandgap reference create and regulate supply voltages rather than switch them.
What output voltage range is supported?
Both LDOs adjust between 0.45 V and 0.9 V in 50 mV increments. They run from a 1.2 V core supply that can sit anywhere from 1.08 V to 1.32 V. The bandgap reference takes 1.0 V ±10% and holds a fixed 0.45 V output.
Related
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