Memory Compilers
Embedded memory compilers: SRAM, register file and ROM
Silvaco memory compilers build SRAM, register file and ROM instances to fit your SoC, for design teams who’d rather configure on-chip memory than design around a catalog part.
Choose the memory type, then configure it
A catalog instance arrives with its area and leakage already decided, and you pay for those decisions at integration. A
compiler works the other way round. You set the words, width, mux and power modes, and it builds the instance to
match. That’s why one Silvaco memory compiler covers designs as far apart as an AI
accelerator and a wearable.
Single and dual port SRAM
General-purpose read-write memory in low-power, general-purpose and high-performance variants. At 55 nm and below, nap and retention modes cut leakage while the core holds its data. Run periphery and core from one supply or two, and add a write mask if you need it.
Catalog: 12 compilers · 7 single-port, 5 dual-port · TSMC, GlobalFoundries, UMC · 22–130 nm
1 and 2 port register file
Small, fast arrays that sit right next to the logic, on a Silvaco-proprietary architecture built for density and low power. Standby, retention and shutdown modes trade wake-up time against leakage, and byte-mode writes change part of a word without touching the rest.
Catalog: 5 compilers · 3 one-port, 2 two-port · TSMC, GlobalFoundries · 22–110 nm
ROM
Code and fixed data, programmed on a single via layer to keep the array dense and the die cost low. The array itself doesn’t leak. Column mux runs from 8 to 128.
Catalog: 2 compilers · TSMC ULP eFlash · 40 and 55 nm
Memory compiler selector
Find the compilers for your foundry and node, with the size range and mux options each one generates.
GF = GlobalFoundries. Size runs from the smallest to the largest instance a compiler generates, in bits. Mux is column
multiplexing. Retention marks a data-retention mode, and a dash means there’s no separate array supply.
Applications
Where compiled memory goes, on mature nodes and advanced ones alike.
Edge computing and IoT low-power designs
Low-leakage sleep modes for battery-powered parts, alongside Low Power Foundation IP
Industrial automation, process control and robotics
Memory on the high-voltage, BCD and eFlash processes industrial parts are built on
Display drivers and DDICs
SRAM and register files inside the driver IC
Security and cryptographic processors
SRAM for working data, ROM for fixed code
Audio and voice processing ASICs
Low-leakage buffers for always-listening designs
Qualify it from published data
Part numbers, foundries and nodes are all on the record, so your IP
qualification can start before the first call.
19 compilers
each with a part number in the PRO IP catalog, 61250 to 61268
TSMC · GlobalFoundries · UMC
the foundries in the current catalog
22–130 nm
from GlobalFoundries 22FDX to TSMC 130 nm BCD
25+ years
building compiled memory, with silicon in thousands of designs
Liberty · LEF · GDSII
delivered with every characterized, DRC/LVS-clean instance
Catalog · PDF
Summer 2026
IP product selection guide
Every memory compiler by foundry, node and part number, next to the rest of Silvaco’s licensed IP.
Webinar
Summer 2026
How to Design Ultra-low Power Embedded Memories with Silvaco Memory Compilers
The architecture behind the three compiler types, and where their density and leakage figures come from.
Webinar
Summer 2026
Achieving Extreme Low Power IoT Designs with Silvaco’s 55LPx Foundation IP Solution
Low-power foundation IP on GlobalFoundries 55LPx, the same process as compiler 61263.
News
Summer 2026
Silvaco Acquires Memory Compiler Technology of Dolphin Design SAS
Where the compiler line came from, and the quarter-century of low-power memory work it brought with it.
What can the compiler build on
your process?
Send an IP specialist your foundry, node and memory type. You’ll get a technical briefing on
configuring the compiler for your application, plus licensing and availability for that process. If
the standard options don’t reach your targets, the compiler team can tune an instance to your PPA
numbers.
Memory compiler questions
What is a memory compiler?
A memory compiler is software that generates on-chip memory instances to a specification: number of words, word width, column mux and power options. You get a layout and a full set of models for exactly that instance. Silvaco’s compilers build single- and dual-port SRAM, 1- and 2-port register files and via-programmed ROM.
What is the difference between SRAM, register file and ROM?
SRAM is general-purpose read-write memory with one or two ports. A register file is a smaller array, also with one or two ports, used for fast local storage. ROM holds code or data that never changes, programmed on one via layer. Designing standalone DRAM or NAND instead? See Logic and Memory.
Which foundries and nodes are supported?
The current catalog lists 19 compilers: TSMC at 40, 55, 90, 110 and 130 nm, including eFlash, high-voltage and BCD processes; GlobalFoundries 22FDX, 22FDX+ and 55LPx; and UMC 110 nm eFlash. If your process isn’t on that list, the compiler team can port to other nodes.
What deliverables does a compiler generate?
Each instance is foundry-qualified and comes with Liberty timing and power models, LEF abstracts and GDSII layout, all characterized and DRC/LVS-clean. Those are the views your flow reads to place, route and sign off the memory, generated for the exact configuration you chose.
What is BIST and repair support?
Built-in self-test (BIST) lets a chip test its own memory after manufacture, and repair swaps failing locations for spare ones. Both are optional on the SRAM and register file compilers. ECC bits, plus flexible word size and addressing, give you room to build in redundancy.
How is a compiler licensed?
You license the compiler rather than a single instance, and each catalog part number covers one foundry process. So you can generate whatever configurations each design needs, from one instance to dozens. Ask an IP specialist about terms for your node.
Related IP
SRAM Compiler
Single- and dual-port read-write memory with low-leakage modes.
Register File Compiler
1- and 2-port arrays with byte-mode writes.
Foundation IP
Memory compilers, standard cells and interface IP.
ROM Compiler
Via-programmed ROM, column mux from 8 to 128.
Standard Cell
Logic libraries for TSMC, GlobalFoundries and UMC processes.