Register File Compiler
1 and 2 Port Register File Compilers
Register file compilers from Silvaco build 1-port and 2-port register file IP to your word count, width and mux, for SoC teams who’d rather license small on-chip memory than design it.
What you set, and what comes back
You set the array. The compiler returns a characterized instance
with Liberty, LEF and GDSII views, ready for your flow.
Architecture
Silvaco’s own architecture puts density and low power first, which keeps the macro small. The array is partitioned, it supports embedded switches, and Standby, Retention and Shutdown modes are built in.
Configuration
Run a single supply, or split the rails between periphery and core. You set word width and mux per instance. Byte-level writes, a data retention mode and optional built-in self test and repair (BIST/R) round it out.
Optimization
Choose the low-power, general-purpose or high-performance variant. Then tune speed against leakage with a choice of threshold voltages (multi-Vt) and operating modes.
Yield
Instances are verified for tolerance to global and local variation. ECC bits and flexible word size and addressing leave room for redundancy.
Process coverage
The compiler technology is available from 180 nm down to 22 nm: 180, 152, 130, 110, 90, 85, 65, 55, 40, 28 and 22 nm. It covers G, LP and SOI CMOS, plus high-voltage, BCD and eFlash foundry processes. Five compilers are in production today, each with its own part number. Need a node that isn’t among them? Silvaco can port the compiler to it.
Four power modes, from full speed to off
The deeper the mode, the less the array leaks and the longer it
takes to wake. Match each idle period to the mode it can afford.
| Mode | Core | Periphery | State | Wake-up | Leakage vs Standby |
|---|---|---|---|---|---|
| Active | On at Vdd | On at Vdd | Reads and writes. Dynamic power plus a small leakage. | — | — |
| Standby | On at Vdd | On at Vdd | Powered, no access. No dynamic power. | Quick | 1.00× |
| Retention | Below Vdd | Off | Core held at the minimum voltage that keeps its data. | Slow, while the periphery powers back up | 0.54× |
| Shutdown | Off | Off | Core and periphery off. Contents are lost. | Slowest | Lowest |
The operating modes cut power consumption by up to 50%.
Where register file IP fits
Small on-chip memories and pipeline registers
Arrays from 64 bits, sized to sit beside the logic that reads them.
Low-power embedded designs
Retention holds data at 0.54× Standby leakage, and Shutdown switches off core and periphery.
Designs where SRAM overhead is too high
A density-first architecture keeps the footprint down on arrays too small to justify an SRAM.
Multi-port access requirements
Separate read and write ports on the 2-port compilers, available on TSMC 55 nm HV and ULP eFlash.
Register file compilers in the current catalog
Five compilers, each tied to one foundry process and one part number. Quote the part number when you ask about licensing.
| FOUNDRY | PROCESS | MEMORY TYPE | RETENTION | SIZE (BITS) | MUX | SUPPLY (V) | PART NUMBER |
|---|---|---|---|---|---|---|---|
| GlobalFoundries | 22 nm FDX | 1-port register file | No | 128–40k | 8 | 0.8 | 61250 |
| TSMC | 55 nm ULP eFlash | 1-port register file | Yes | 64–32k | 2, 4 | 1.2 | 61256 |
| TSMC | 55 nm HV | 2-port register file | No | 1k–640k | 4 | 1.2 | 61257 |
| TSMC | 55 nm ULP eFlash | 2-port register file | No | 128–64k | 4 | 1.2 | 61258 |
| TSMC | 110 nm HV | 1-port register file | No | 128–20k | 4, 8 | 1.5 | 61265 |
Sizes are in bits. Process not listed? An IP specialist will scope the port.
Proof and resources
Silvaco’s compiled memory is silicon-proven across
thousands of designs and on millions of wafers.
25 years
of compiled memory design
12
foundries and IDMs where the compilers are deployed
180–22 nm
technology nodes available
0.54×
Retention leakage, against Standby
Up to 50%
lower power across operating modes
Catalog · PDF
Summer 2026
Silvaco IP catalog
The five register file compilers by foundry, process and part number, with retention, size, mux and supply for each.
Webinar
Summer 2026
How to Design Ultra-low Power Embedded Memories with Silvaco Memory Compilers
A recorded session for teams whose memory budget is set by leakage.
News
Summer 2026
Silvaco Acquires Memory Compiler Technology of Dolphin Design SAS
Where the compilers came from. Dolphin Design had supplied ultra-low power, high-density memory compilers for more than 25 years.
Ask about your node
Bring your foundry, your process and the array you need: words, width, ports and power modes.
You’ll hear whether a compiler already exists there, what a port would take,
and how licensing works.
Register file compiler questions
What is a register file compiler?
A register file compiler turns a few parameters (number of words, word width, mux) into a finished register file memory instance. The Silvaco versions make 1-port and 2-port instances on a density-first, low-power architecture. Every instance is characterized and DRC/LVS-clean on its foundry process, and comes with Liberty, LEF and GDSII views.
When should a register file be used instead of an SRAM?
Register files usually suit small, frequently accessed arrays that sit close to the logic, such as pipeline registers. Silvaco's register file architecture is built for density and low power, which keeps those small arrays compact. For a borderline array, an IP specialist can compare register file and SRAM instances on your process.
What is the difference between 1 port and 2 port?
On a 1-port register file, reads and writes share one port, so any given cycle does one or the other. A 2-port register file gives reads and writes a port each, so one address can be read while another is written in the same cycle. The current catalog has three 1-port compilers and two 2-port compilers.
Which nodes and processes are supported?
The compiler technology covers 180 nm to 22 nm, across G, LP and SOI CMOS and high-voltage, BCD and eFlash processes. Five compilers are in the current catalog, at GlobalFoundries 22FDX and TSMC 55 nm and 110 nm. For any other node, an IP specialist can scope a port.
What power modes are available?
Four: Active, Standby, Retention and Shutdown. Standby stays powered but idle and wakes fast. Retention cuts the periphery and holds the core at the lowest voltage that keeps data, at 0.54× Standby leakage, and Shutdown turns both off and loses whatever was stored.
What does byte mode do?
With byte mode, a write changes only the bytes you select. The rest of the word stays as it was, so your logic can update part of a word without reading it back first. It's a register file compiler write option, so confirm it for the compiler and process you plan to license.
Related IP
SRAM Compiler
Single- and dual-port SRAM instances
ROM Compiler
Read-only memory from the same compiler family
Memory Compilers
The SRAM, register file and ROM compilers side by side
Foundation IP
Standard cell libraries, I/Os and ESD, and memory compilers