SURGE Virtual Event North America 2022
Concluded event
SURGE Virtual Event North America 2022
North America · Thursday, October 27, 2022 · Virtual event
At a glance
October 27, 2022
Date
North America
Region
Virtual
Format
24
Sessions in 3 tracks
About this event
The general session at SURGE North America 2022 gave two of its three slots to guests. Prof. Giovanni De Micheli of EPFL spoke on superconducting circuit design, and Patrick Groeneveld of Cerebras on mapping machine learning models onto a chip the size of a wafer.
SURGE is where engineers who work in Silvaco’s TCAD, EDA and IP tools meet once a year. People outside Silvaco gave twelve of the 24 talks. Among them: Wolfspeed on silicon carbide mobility, Intel on I3C debug, PsiQuantum on quantum computer SoCs, and modeling work from Purdue and TU Wien. Silvaco engineers gave the other twelve, including the year’s updates on TCAD, analog custom design and Design IP.
Date
- General Session
- TCAD Track
- EDA Track
- IP Session
Agenda
All 24 SURGE North America 2022 recordings are archived on Silvaco’s support site. Log in
with a support account, or register with a corporate, university or government email
address. Free email addresses aren’t accepted.
General Session
Dr. Babak Taheri
CEO and Board Member, Silvaco, Inc.
Speaker bio, October 2022
He came to Silvaco as chief technology officer and executive vice president of products, and went on to lead it as CEO. Before that he ran the sensor solutions business at Freescale, now NXP. At Cypress Semiconductor and InvenSense (now TDK) he was a vice president and general manager, and earlier he worked at SRI International and Apple. His PhD, in biomedical engineering, is from UC Davis. He holds more than 30 issued patents.
Design and Optimization of Superconducting Circuits
Prof. Giovanni De Micheli, École Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Abstract
Superconducting electronics (SCE) can speed up computation, and it suits data-flow designs and machine learning algorithms well. The hard part is logic design, because every superconducting circuit style imposes constraints of its own. Prof. De Micheli connects those styles and constraints to synthesis, as groundwork for building SCE tool flows in more than one way. He closes on recent results.
Speaker bio, October 2022
Professor at EPFL, where he directs both the Institute of Electrical Engineering and the Integrated Systems Centre.
Designing Extreme Scale Machine Learning Hardware
Patrick Groeneveld, Ph.D, Cerebras Systems
Abstract
Machine learning runs on custom ASICs at every scale: a few milliwatts in a phone, a dozen watts in a car, many kilowatts to train a large model. Cerebras built the top of that range. Its Wafer Scale Engine, a single ASIC with 2.4 trillion transistors, drives an ML supercomputer. Dr. Groeneveld traces how the software takes a PyTorch model and places it on that chip. There’s synthesis, placement and routing, as in any ASIC flow, except the target here is an entire wafer.
Speaker bio, October 2022
Before Cerebras he spent many years in EDA, including as Magma Design Automation’s Chief Technologist, on the team behind its RTL-to-GDS2 synthesis product. He has held a full professorship at Eindhoven University, in electrical engineering. He also lectures in Stanford’s EE department and chairs finance on the Design Automation Conference’s executive committee. MSc and PhD from Delft University of Technology.
TCAD Track
TCAD Simulation Update
Dr. Eric Guichard, Silvaco, Inc.
Abstract
The state of Silvaco’s Victory TCAD simulation products in October 2022. Dr. Guichard also explains what TCAD contributes while a new device is still in development, and which way TCAD development is headed.
Speaker bio, October 2022
He runs all of Silvaco’s TCAD work, from R&D through field operations. Since joining in 1995 he has directed Silvaco France and, later, worldwide TCAD field operations. Before Silvaco he was a senior SOI engineer at LETI and at Thomson Military and Space, studying transistor and circuit aging. His MS, in materials science, and his PhD, in semiconductor physics, are both from the Ecole Nationale Polytechnique de Grenoble.
Products: TCAD
Revised Mobility Model for Predictive TCAD Simulations of 4H-SiC
Hemant Dixit, Ph.D., Research Scientist, Wolfspeed, Inc.
Abstract
SiC power MOSFETs go into energy storage, industrial motor drives, electric vehicles, power supplies and solar inverters. Each new generation has to waste less energy, and getting there depends on predictive TCAD. For 4H-SiC, the models still need work. Dr. Dixit starts with bulk mobility. The usual mobility models can’t predict how bulk resistivity changes with temperature, because they leave out the impurity scattering that dominates at low temperature. The talk replaces them with one complete, calibrated bulk mobility model for 4H-SiC. It tracks measured data closely enough for device simulation in TCAD.
Speaker bio, October 2022
At Wolfspeed he works to deepen the physical understanding of power MOSFETs, after earlier roles at Motorola, IBM and GLOBALFOUNDRIES. His modeling runs from the atomistic to the continuum scale. More than 35 research articles with over 1,700 citations, and 15 US patent applications, 6 granted. PhD in physics from the University of Antwerp.
Products: TCAD
TCAD as a Key Enabler for Photodiode Design
Sungwon Kong, Silvaco, Inc.
Abstract
Vision systems in cars, industrial machinery and high-speed communications links all depend on a photodiode turning light into a usable electrical signal. Detectors vary in topology and material, and TCAD applies across many of them, which opens it to many end markets. The worked case is an InGaAs avalanche photodiode. Sungwon Kong simulates and analyzes it, then extracts its key figures of merit. You see how TCAD lifts detector performance while cutting engineering, manufacturing and test cycles.
Speaker bio, October 2022
Senior staff field applications engineer. He has supported TCAD for digital displays since 1996, starting at Silvaco Korea, and worked at Samsung Electronics in Giheung before that. He studied electrical materials and device engineering at Inha University.
Products: TCAD
Advanced Flux Models in Victory Process: Low-Bias SF6 Etching and Thermal Atomic Layer Processing
Luiz Felipe Aguinsky, Researcher, Christian Doppler Laboratory for High Performance TCAD, Institute for Microelectronics, TU Wien
Abstract
Some processes are driven by one uncharged particle: low-bias SF6 etching, for instance, or thermal atomic layer deposition and etch. Even these need careful physics before their topography can be predicted. Particle fluxes and surface kinetics together decide the result. Luiz Felipe Aguinsky surveys phenomenological process TCAD models that track a single particle, and shows how much the choice of flux model changes the simulated profile. He covers the flux models already in Victory Process alongside advanced ones from the Christian Doppler Laboratory. For low-bias SF6 etching, a Monte Carlo method is being prototyped inside Victory Process. For thermal atomic layer processing, a one-dimensional Knudsen-Langmuir model is built entirely in the Open Model Library, proof that you can extend Silvaco TCAD with models of your own.
Speaker bio, October 2022
A doctoral researcher at TU Wien’s Institute for Microelectronics since March 2018, due to take up a Schrödinger Fellowship at ETH Zurich. He studied physics at the Federal University of Rio Grande do Sul, then simulation sciences at RWTH Aachen, with a master’s thesis written at the German Aerospace Center. His research covers process TCAD models, atomic layer processing and devices such as valence-change memories.
Products: Victory Process
Behavior of FinFET at Very Low Temperatures and Creation of Qubits
Sanam Moslemi-Tabrizi, Hardware Engineer, Ciena
Abstract
Two needs brought Ciena to atomistic simulation. The supplied models behind its analog design lose accuracy as devices scale, because classical tools can’t see the quantum effects that take over. And its qubit research needs device behavior at cryogenic temperatures, which the team could measure, but only at high cost and with a complex process. Quantum device modeling calls for a tool that solves the Poisson and Schrödinger equations together, self-consistently. Victory Atomistic (ViA) met that bar, and close work between the Silvaco and Ciena teams filled in the details. ViA now reproduces Ciena’s lab results for its in-house 5nm devices at room temperature. For the qubit research, the aim is to replace cryogenic measurement with simulation. Future work improves ViA on several fronts, starting with convergence deep in the cryogenic range.
Speaker bio, October 2022
An analog engineer at Ciena, optimizing analog circuits and building quantum device models for the company’s future products. At Carleton University she researched electromagnetics, including OPA-based 2D beam scanning for LiDAR, and wrote a Yee-cell FDFD mode solver and waveguide simulator. Her master’s research at Concordia computed eigenstates of multi-dimensional nanostructures.
Products: Victory Atomistic
Performance Improvement for Cu Interconnects by SAM and ELD Technologies
Yuki Kikuchi, Tokyo Electron Limited
Abstract
Better copper interconnects in the BEOL, from two selective techniques. A SAM deposits only on chosen materials, and ELD grows metal only where it’s wanted. Combined, they improve device properties. Tokyo Electron’s experiments and the Silvaco simulations show the same trend, which makes the case for the process.
Speaker bio, October 2022
Joined Tokyo Electron in 2011, straight from the University of Tsukuba. He works in Corporate R&D on fundamental technology, BEOL processes, 3DI and process integration.
Victory Atomistic - Updates on 2D Materials, CNTs, and How We Bridge Atomistic Simulations and TCAD
Tillmann Kubis, Purdue University
Abstract
A useful prediction for a nanodevice needs atomistic resolution, a consistent account of every quantum effect, and realistic incoherent scattering off phonons and impurities. Atomistic quantum transport is widely assumed to cost too much compute or to leave scattering out. Victory Atomistic handles all three, and Prof. Kubis presents its new modeling features for 2D materials and carbon nanotubes. Some atomistic runs still need a few CPU hours, so Silvaco and Purdue are connecting atomistic simulation to TCAD. The aim is answers you can rely on, in the run times TCAD users expect.
Speaker bio, October 2022
Leads Purdue’s NEMO5 development team and holds the Katherine Ngai Pesic and Silvaco Research Associate Professorship in electrical and computer engineering. His research covers electronic and phonon bandstructures, and how heat, charge and spin move through nanodevices. He earned his Dr. rer. nat. at TU München, in theoretical semiconductor physics.
Products: Victory Atomistic
Achieving Accurate Experimental Etch Profiles in FinFET and Memory Applications with Victory TCAD Solution
Alexander Toifl, Silvaco, Inc.
Abstract
Building a complex device structure in process simulation often comes with a hard requirement: match the etch profile the fab actually produced, as seen under the transmission electron microscope. Victory Process has several geometric etch models that get there efficiently. Alexander Toifl puts them to work on FinFET and memory structures, shaping fins, reproducing non-ideal profiles with bowing and twisting, and running self-aligned multi-patterning.
Speaker bio, October 2022
A development engineer who has worked on Victory Process etch and deposition models since joining Silvaco in 2021. Both his doctorate in electrical engineering and his master’s in microelectronics and photonics are from TU Wien.
Products: Victory Atomistic
EDA Track
Analog Custom Design Update
Thomas Blaesi, Silvaco, Inc.
Abstract
Thomas Blaesi covers what’s new in Silvaco’s analog custom design tools, then sets out the EDA roadmap.
Speaker bio, October 2022
Responsible for developing Silvaco’s EDA tools, among them circuit simulation, SPICE modeling and analog custom design. He joined in October 2017 and ran global marketing until December 2019. Earlier he was managing partner at Zeema Technologies and CEO of Chipvision, after senior business and technical roles at Cadence, Synopsys and LSI Logic. He studied electrical engineering and computer science at Hochschule Furtwangen University (BS).
Products: Analog and Custom IC
Advances in Device Modeling Using Utmost IV
Bogdan Tudor, Silvaco, Inc.
Abstract
The 2022 Baseline release of Utmost IV added the Corner and Retargeting Module to Silvaco’s device modeling platform. Bogdan Tudor shows it, then turns to recent models and technologies where Utmost IV played a part. He finishes with Silvaco’s SPICE modeling services, for teams that would rather hand the modeling work over.
Speaker bio, October 2022
Leads the Utmost and modeling services teams as Silvaco’s head of device characterization, with more than 20 years building model development and characterization software.
Products: Utmost IV
A Robust 3nm to 350nm Design Flow Utilizing Silvaco Tools
Chung-Chun Chen, Director of Analog Design, Silicon Creations
Abstract
Silicon Creations sells IP across a wide spread of processes, and this is its flow through Silvaco tools. On the front end, Gateway handles porting between 12 foundries, at nodes from 180nm down to 3nm. Expert covers the back end. Simulation runs in SmartSpice, Silos and Variation Manager. Chung-Chun Chen takes each stage’s challenges in turn, and shows the flow keeping IP development efficient from 3nm to 350nm.
Speaker bio, October 2022
SerDes IO principal circuit architect at Silicon Creations, where he has designed ring and LC-tank PLLs, serializers, deserializers and their clocking and equalization blocks. He spent 2018 to 2019 as the architect of Realtek’s high-speed SerDes at Ubilinx Technology. Earlier stops: Samsung Electro-Mechanics’ Atlanta design center and TSMC, on clocking architecture. More than 15 peer-reviewed papers; reviewer for JSSC and T-MTT.
Products: Gateway, Expert, SmartSpice, VarMan
Products: Analog and Custom IC, Design IP
Advanced TFT-Based Flat Panel Design with SmartSpice
Jody Matos, Silvaco, Inc.
Abstract
Two problems in flat panel display design: TFTs with four terminals, and image retention. A good share of today’s TFT technologies use a fourth terminal, and Silvaco’s four-terminal TFT compact model is built for them. Dr. Matos describes how the model behaves and the extra room it gives modeling and design teams. Image retention has troubled displays for years. To fix it, or even limit it, display makers and consumer electronics companies have to simulate it at the SPICE level. SmartSpice Flex Modeling handles that simulation, along with other dynamic device effects.
Speaker bio, October 2022
Director of Circuit Simulation, leading Silvaco’s R&D and business projects on circuit simulation and analysis for analog, digital and mixed-signal designs. PhD in computer science and MS in microelectronics, both from UFRGS in Brazil. Co-author of more than 30 papers and patent applications.
Products: SmartDRC/LVS
Silvaco SmartDRC/LVS: A Powerful, User Friendly and Flexible Layout Verification Solution
Richard Lum, CEO, MPics Innovations
Speaker bio, October 2022
Co-founder and CEO of MPics Innovations, a custom analog circuit design and manufacturing company, where he is also the chip architect. Before MPics he directed R&D, as senior director, in Broadcom’s Isolation Products Division. He also built up IC design operations in Singapore on behalf of Aztech Systems and BlueChips Technology. He holds more than 20 patents in analog circuits and isolation, and has filed one for an isolation method suited to GaN and SiC power devices. B.Eng from the National University of Singapore; MBA from the UK Open University.
Products: SmartDRC/LVS
VarMan Delivers Unprecedented High-Sigma Performance within a User-Friendly GUI Environment
Vincent Annezo, Silvaco, Inc.
Abstract
VarMan has been deployed worldwide for years, and customer feedback from all that use shaped this release. It brings a redesigned GUI and improved algorithms, and keeps the accuracy and flexibility VarMan is used for. The aim is variation analysis that a wider group of your engineers can pick up.
Speaker bio, October 2022
Corporate application engineer focused on improving and supporting VarMan. Before Silvaco he spent nine years in software validation and applications at Aselta, a French EDA start-up. Master of Engineering in physics from INSA Rennes.
Products: VarMan
Latest Update on Interconnect Parasitic Reduction and Analysis with Jivaro and Viso
Simon-Alexis Abric, Silvaco, Inc.
Abstract
Post-layout parasitics slow SPICE simulation, and advanced process nodes slow it most. Jivaro’s new Pro module reduces the parasitic network so those simulations run much faster. Viso works the other side of the problem. Its new features let you understand and debug parasitic structures directly, before you commit to a long simulation.
Speaker bio, October 2022
Corporate application engineer at Silvaco France, supporting customers on Jivaro parasitic reduction and Alps parasitic analysis. He spent four years as an application engineer at Edxact before Silvaco. Master of Engineering in integrated circuits and systems from ENSEIRB, Bordeaux, 2013.
Products: Jivaro Pro, Viso
IP Session
Design IP Solutions Update
Ben Louie, Silvaco, Inc.
Abstract
Ben Louie reviews Silvaco’s Design IP portfolio and the direction Silvaco is taking it.
Speaker bio, October 2022
Associate vice president of foundation IP. Before Silvaco he directed memory design at Spin Memory, where he was a Fellow and one of the primary inventors of its MRAM Engine IP. At Zeno Semiconductor he led design on a novel 1T SRAM. His earlier career took in Magsil, Xilinx and Micron, where he was design lead on the company’s first NAND products. Both his degrees in electrical engineering, bachelor’s and master’s, are from Santa Clara University. He has more than 116 issued US patents.
Products: Design IP
Challenges of Designing Quantum Computer SoCs
Jack Berg, VP of Operations, PsiQuantum
Implementing Debug for I3C
Ashish Senapati, Platform Debug Architect, Intel
Abstract
Debug, trace and failure analysis over an I3C bus, with no extra pins. The Simplified Address-Mapped (SAM) debug add-on for I3C carries data from the application to the peripheral under debug, and back, on the bus’s existing SCL and SDA lines. Ashish Senapati details the add-on IP and how it connects to common debug and trace adapters: ARM DAP, ARM-ETM/SWO, JTAG-TAP and RISC-V DMI/DM.
Speaker bio, October 2022
Platform debug architect in Intel’s Client Computing Group. He spent ten years at Microchip Technology as an SoC architect for low-power 8-bit and high-performance wireless microcontrollers. Before that, three-plus years building microcontroller and FPGA demos and proof-of-concept designs for Altera, Microchip and Freescale.
Products: I3C
Replacing an End-of-Life MCU
Errett Hogrefe, Senior Digital Design Engineer, Silvaco, Inc.
Abstract
Every microcontroller reaches end-of-life. If your product carries years of software written for one MCU, moving it to another part is rarely simple. One answer is to build a functional replacement of your own, and Errett Hogrefe covers the design considerations and implementation choices along that path. Each replacement is a custom project that draws on a range of IP, and Silvaco supplies both IP products and design services for it.
Speaker bio, October 2022
Senior digital design engineer on Silvaco’s IP team since 2017. He architects, develops and supports many of its digital cores, SPI, Quad-SPI and Octal-SPI controllers among them. Before that he spent 16 years in engineering roles at SoC Solutions.
Standard Cells and I/O Library Optimization and Validation
Mr. Faris Amsyar Bin Ahmad Zhaki, IP Staff Engineer, SilTerra Malaysia Sdn. Bhd
Abstract
SilTerra keeps developing and enhancing its processes, so its standard cell and I/O libraries must be re-optimized and re-validated to match. For a small team, that load adds up. Faris Amsyar walks through where that work gets difficult and shows Cello, Viola and SmartSpice each taking a share of it, so library development and validation finish sooner.
Speaker bio, October 2022
IP staff engineer at SilTerra, where he has spent more than five years building cell and I/O libraries and proving them in silicon. Bachelor of Electronics Engineering from the University of Science, Malaysia.
Products: SmartSpice, Standard Cell
Cello FinFET Standard Cell Synthesis
Dan Fitzpatrick, Silvaco, Inc.
Abstract
FinFETs gave chip designs more density and performance at lower power than planar layouts did. They also made standard cell design rules far harder. A violation often can’t be fixed where it sits: it spreads across a large part of the cell and involves many layers. That slows the first layout, every migration to a new node and any specialization of the library. Dan Fitzpatrick picks out the hardest parts of FinFET standard cell layout and shows how Cello FinFET handles them.
Speaker bio, October 2022
Leads IP software development for Silvaco’s Design IP group in Santa Clara as associate VP, building the tools used to design, characterize and manage IP. His Master of Science in Engineering is from the University of Florida.
Products: Standard Cell, Cello FinFET
Themes at SURGE North America 2022
Wolfspeed’s SiC mobility model, an InGaAs photodiode, Victory Process etch and flux models, and atomistic work with Ciena and Purdue
SmartSpice on four-terminal TFTs and display image retention, and in Silicon Creations’ flow
SmartDRC/LVS at MPics, VarMan’s redesign, and parasitics in Jivaro Pro and Viso
Library validation at SilTerra and FinFET cell synthesis in Cello
Intel on I3C debug, a replacement for an end-of-life MCU, and the Design IP update
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