Concluded event

SURGE Virtual Event Japan 2022

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At a glance

November 15/2022

Date

Japan

Region

Virtual

Format

12

Sessions in 1 tracks

SURGE (Silvaco UserRs Global Event) is a worldwide event hosted by Silvaco.
SURGE is an event where new technologies are discussed, user experiences are shared, and innovative technologies for advanced semiconductor design are discovered in the fields of TCAD, EDA, and IP.

You can watch videos of the lectures from the day on demand, with the exception of some of the lectures.
A Silvaco account is required to view. (If you don’t have one, please take this opportunity to register.)

Date

  • presentation

Agenda

presentation

Silvaco Update (English)

Dr. Babak Taheri, CEO, Board Member,

Dr. Babak Taheri serves as CEO and Board Member of Silvaco, a leading company in TCAD, EDA, and design IP software, and previously served as CTO and Senior Vice President of Product at Silvaco. Prior to Silvaco, he served as CEO and President of IBT, working with investors, private equity firms, and M&A, technology, and business startups.

At IBT, he served as an advisor to MEMS World Summit, Novasentis, AGCM, ALEA Laboratories, Lion Point Capital, and Silver Lake. He also served as Executive Vice President of the Sensor Solutions business unit at Freescale Semiconductor (now NXP).

He received “The Perfect Project Award” from Cypress in 2003 and the “Diamond Chip Award” twice from Freescale in 2013 and 2014. He received the MEMS & Sensors Executive of the Year Award from the UC Davis School of Engineering in 2014 and the Distinguished Engineering Alumni Medal in 2015, and currently serves as an advisor to the UC Davis School of Engineering. Dr. Taheri served on the Governing Board of the ESDA Alliance from 2019 to 2021 and as a director of Parisi House on The Hill from June 2021 to May 2022.

Dr. Babak Taheri has also served as Executive Vice President at Cypress Semiconductors and Invensense (now TDK), and held key positions at SRI International and Apple. He received his Ph.D. in Biomedical Engineering with a major in EECS and Neuroscience from UC Davis. He has published over 20 papers and holds more than 30 patents. In 2021, he published a book titled “Artificial Sensors Shape the Six Pillars of Our Lives.”

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Keynote Speech: Semiconductor Industry Policy and the Path to Japan's Semiconductor Revival

Mr. Masao Taguchi, MT Electro Research

He joined Fujitsu Laboratories in 1976 and engaged in semiconductor device research. From 1988, he worked at Fujitsu on the development and design of advanced DRAM, handling analog circuits such as memory cells, high-speed input/output circuits, and power supply circuits. In 2003, he became Chief Scientist of FASL LLC, a joint venture between Fujitsu and AMD, and led the US development team in the development of ReRAM (resistive random-access memory) technology. From 2007, he served as President and CEO of Spansion Japan, and in 2009, he was appointed as a management trustee for the company’s restructuring. After serving as a technical advisor to Elpida Memory, he became a specially appointed professor at Keio University in October 2011, and a researcher at the university’s Research Center for Advanced Science and Technology in April 2017. He heads MTElectroResearch, which undertakes technology development and consulting.
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Silvaco TCAD Update

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Performance improvement for Cu interconnects by SAM and ELD technologies.

Mr. Yuki Kikuchi, Tokyo Electron Limited

Graduated from the Yamabe-Hasunuma Laboratory, Graduate School of Engineering, University of Tsukuba in 2010 (Semiconductor FEOL field). Joined Tokyo Electron Limited in 2011. 12 years of service. Currently in the Corporate R&D Department. Engaged in elemental technologies, BEOL processes, 3DI, and process integration development. (Recipient of the Tokyo Electron Group Outstanding Employee Award in 2021)
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Introduction to Student Experiments for Third-Year University Students Using the Victory Tool

To Professor Tsugutomo Kudo, Kanagawa Institute of Technology

1998: Completed Master’s program in Engineering at Tohoku Gakuin University Graduate School. 1998: Joined Dai Nippon LSI Design, Ltd. 2005: Completed doctoral program in Information Engineering at Kyushu Institute of Technology Graduate School. Same year: Assistant Professor, Department of Electrical and Electronic Engineering, Faculty of Engineering, Kanagawa Institute of Technology. Subsequently served as Assistant Professor and Associate Professor, and in 2021 became Professor, Department of Electrical and Electronic Information Engineering, Faculty of Engineering, Kanagawa Institute of Technology.
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Kaoru Kashimura, Senior Application Engineer, IP Business Unit, Silvaco IP Update

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Implementing Debugging for I3C (English)

Ashish Senapati, Platform Debug Architect

Ashish Senapati is a Platform Debug Architect working in Client Computing Group at Intel Corporation. He has 10 years of experience as an SOC Architect for low power 8-bit microcontrollers and high performance wireless microcontrollers at Microchip Technology Inc. Prior to that he worked for 3+ years in application development using microcontrollers and FPGAs for CES demos and proof of concept designs for Altera (Intel), Microchip and Freescale (NXP).
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Standard Cells and I/O Library Optimization and Validation (English)

Nur Liyana Binti Jasn, IP Staff Engineer

Ms. Nur Liyana Binti Jasni is an IP Staff Engineer with SilTerra focusing on Standard Cell and I/O library development and silicon validation for over 11 years. Ms. Nur Liyana Binti Jasni holds a Bachelor of Science in Electronics & Computer Engineering from Hanyang University, South Korea.
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X-FAB Process and PDK Support,

Mr. Kenji Nanba, Field Application Engineering Manager, X-FAB Japan

Graduated from the Department of Physics, Faculty of Science, Osaka University . Received a PhD in Engineering from the Graduate School of Engineering Science, Osaka University . Joined Texas Instruments Japan in 1996, where he was involved in basic research, circuit design, and ESD review. Joined X-FAB Japan in 2009, where he has worked as a Field Engineering Engineer (FAE) to the present.
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Application of CAAC-IGZO FETs to LSIs

Mr. Shin Ishikawa, System Development Department Leader, Semiconductor Energy Laboratory Co., Ltd.

He joined Semiconductor Energy Laboratory Co., Ltd. in 2007. He has been involved in semiconductor process development and system development, and is currently the head of the system development department.
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Silvaco EDA Update

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Atsushi Hasegawa, Senior Application Engineer, Silvaco EDA Update ACD

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Related

SURGE 2023, EMEA

November 21, 2023 · Virtual event

SURGE 2023,
Taiwan/Singapore

November 23, 2023 · Virtual event

SURGE 2023, Japan

November 28, 2023 · Live event

Events

The year's trade-show dates, IEDM and TSMC's forums among them