SURGE Virtual Event Taiwan / Singapore 2023

Concluded event

SURGE Virtual Event Taiwan / Singapore 2023

Taiwan / Singapore · Thursday, November 23, 2023 · Virtual event

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At a glance

November 23, 2023

Date

EMEA

Region

Virtual

Format

19

Sessions in 3 tracks

About this event

At SURGE Taiwan/Singapore 2023, Silvaco’s own staff gave just two of the 11 talks. The whole event was one virtual day, Thursday, November 23.

SURGE, short for Silvaco UseRs Global Event, is where people working in TCAD, EDA and IP show what they’ve learned on real projects. They also pick up techniques other teams are trying.

Most of this edition’s outside speakers were researchers. They came from National Yang Ming Chiao Tung University, National Taiwan University, A*STAR’s Institute of Microelectronics, the Ferdinand-Braun-Institut and Macquarie University. Unisantis Electronics, Kepler Computing and STMicroelectronics brought the industry view. Chiping Tu and Zhao Qingda, who head Silvaco’s Taiwan and Singapore offices, opened the day with CEO Babak Taheri.

Agenda

Silvaco’s support site holds a video download of every SURGE Taiwan/Singapore 2023 talk. It
asks you to sign in first, or to fill in your details with a work or university email.

Sessions

Welcome and Introduction

Dr. Babak Taheri, CEO and Board Member, Silvaco, Inc.

Chiping Tu, General Manager, Silvaco Taiwan

Zhao Qingda, Managing Director, Silvaco Singapore

CEO of Silvaco, and a director, for all but two months since August 2019. He first joined in October 2018 as CTO and Executive VP of Products. Before that he led Integrated Biosensing Technologies, an advisory and consulting firm, as its CEO. He holds a PhD in biomedical engineering from UC Davis and has chaired its electrical engineering department’s advisory board.
General manager of Silvaco Taiwan. He joined in 2008 and has been responsible for sales of every Silvaco product in Taiwan since, as well as the local team. He studied at National Taiwan University (BS) and UT Austin (MS), both in electrical engineering.
Managing director of Silvaco Singapore, with sales for Singapore, Australia and Southeast Asia under him. He has been with Silvaco since 2005. Bachelor’s and master’s degrees from Nanyang Technological University’s School of Electrical and Electronic Engineering.
Watch the recording

Machine Learning: A New Revolution for EDA

Patrick Groeneveld, Ph.D.

Between a functional description and a mask pattern sits a long chain of EDA algorithms. Some are numerical solvers. Others are heuristics, kept because they work. Each has parameters engineers tune by hand, trading area against speed through relative costs.

Some newer tools let machine learning find a design-specific parameter set instead. They run the flow over and over and read the gradients out of the PPA results. Research is going further, toward EDA tools built on ML from the start, for placement and for routing. Dr. Groeneveld maps where ML in EDA stands and what it could change over the next ten years.

At Magma Design Automation he was Chief Technologist, on the team that built an RTL-to-GDS2 synthesis product. He has also worked at Cadence, Synopsys and Cerebras. He held a full professorship in electrical engineering at Eindhoven. He now lectures in Stanford’s EE department and is finance chair on the Design Automation Conference’s executive committee. MSc and PhD from Delft University of Technology.
Watch the recording

WBG Semiconductor For EV and AI Data Center

郭浩中 (Hao-Chung Kuo), Chair Professor of NYCU, Director of HHR

His research is in photonics: semiconductor lasers, VCSELs, blue and UV LEDs, and solar cells. It adds up to over 400 journal papers and 45 granted patents. He joined National Chiao Tung University’s Institute of Electro-Optical Engineering in 2002, after Bell Labs, Agilent Technologies and LuxNet. Fellow of the IEEE, OSA, SPIE and IET. PhD from the University of Illinois at Urbana-Champaign.

Recordings for all 20 SURGE North America 2025 talks sit on Silvaco’s support site. To open
one, sign in there or complete a short form with a work, university or government email.

Watch the recording

Novel Dynamic Flash Memory and Key Shape Floating Body Memory

Dr Li Yisuo, Unisantis Electronics Singapore Pte Ltd

Twenty-four years in TCAD, at GlobalFoundries, Synopsys and Global TCAD, and as a co-founder of Cogenda. At Unisantis since 2008, he led Surrounding Gate Transistor research from the 32nm node down to 1.5nm before turning to floating body memory. He holds 46 patents, and in 2021 he published the first 1.5nm-node SRAM paper at IMW.
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TCAD Simulation Update

Dr Li Yisuo, Unisantis Electronics Singapore Pte Ltd

An update on Victory, Silvaco’s TCAD simulation line, from the executive who runs it. Dr. Guichard also explains why TCAD matters to device development, then turns to where TCAD development is going.
He joined Silvaco Data Systems, the subsidiary now called Silvaco SA, in 1995, in roles that included applications engineering. VP of Applications from 2008, then SVP and general manager for TCAD from November 2012. Master’s in materials science and a doctorate in semiconductor physics from the Institut Polytechnique de Grenoble.

Products: TCAD

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Silvaco Simulation Tools Assisting GaN-based Power Devices Design and Development

Dr. Eldad Bahat-Treidel, Senior Scientist, Ferdinand-Braun-Institut

Lateral GaN power devices are close to commercial maturity for switching up to the 650 V class. They still fall short of GaN’s material limit on RDS(on)·A against breakdown voltage, though. Two device routes aim at that gap:

  • Vertical GaN transistors. They take less wafer area and cut RDS(on)·A by an order of magnitude, to 1.0 mΩ·cm². Strain-free homoepitaxy makes thick, lightly doped drift layers possible, for blocking above 1 kV.
  • Lateral HFETs on an AlN buffer. They should confine the channel more tightly, for stronger blocking and less dispersion.

At FBH, Silvaco simulation runs through the design and analysis of both. Dr. Bahat-Treidel works through three cases:

  • GaN fin MISFET conductance, compared with measurement and predicted across geometry and epitaxial layers
  • Edge terminations for vertical devices, engineered with avalanche models and checked against experiment and theory
  • Trapping and detrapping effects that explain dynamic on-resistance in AlN/GaN HFETs
At the Ferdinand-Braun-Institut in Berlin since 2006, first developing high-voltage GaN switching transistors for power electronics and, from 2014, vertical GaN devices. He came to GaN from photolithography: process engineering at Intel, then R&D at Tower Semiconductor. PhD in electrical engineering from TU Berlin.
Watch the recording

Going Beyond CMOS in Memories

Debo Olaosebikan Ph.D., Co-Founder and CEO, Kepler Computing

Kepler Computing works on design beyond CMOS, particularly for memory. Debo Olaosebikan covers why he and his co-founders started it and what it’s building. He also shows how the team simulates its new memories in Silvaco TCAD.
Before Kepler he co-founded Gigster and served as its CTO. While working toward a physics PhD at Cornell, he led the university’s work on an electric silicon laser, and he researched spintronics at IBM Almaden. Winner of the Future Africa Awards’ Best Use of Science prize in 2011.

Products: TCAD

Watch the recording

Layout Design Automation for Heterogeneous Integration

張耀文 (Yao-Wen Chang), Dean & Distinguished Professor National Taiwan University

The economic case for moving on-chip integration to the next node keeps getting weaker, with EUV, masks and design all adding cost. So PPA gains increasingly come from More-than-Moore heterogeneous integration: separately made dies and components, assembled in a System-in-Package or across packages on a PCB.

Laying those out is a different problem from chip layout. Shapes are arbitrary, metal widths and spacing rules vary, and thermal, mechanical, electrical, optical and system-level effects all interact. The traditional chip flow doesn’t handle that well. Professor Chang surveys the integration options, how their layouts are modeled and the automation problems that follow. He then reviews the published techniques and the research questions still open.

Dean of NTU’s College of EECS and a Distinguished Professor of electrical engineering. He was president of IEEE CEDA, the Council on Electronic Design Automation, in 2020 and 2021, the first from outside the US and Europe. He is a Fellow of both the ACM and the IEEE. His NTUplace placers became the engines inside commercial tools from SpringSoft and from Maxeda, a company he co-founded. Synopsys later acquired both.
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TCAD Simulations of HFC-V for Characterization of Various Traps in SiO2/4H-SiC Interface

Dr Lakshmi Kanta Bera, Institute of Microelectronics (IME), Agency for Science, Technology and Research (A*STAR), Singapore

Senior Principal Scientist at IME, working on process integration for SiC power MOSFETs. Before SiC he worked on GaN-on-silicon and GaN-on-sapphire HEMTs and LEDs. Earlier still came advanced CMOS work at IME, and 40nm logic device design at SilTerra and Chartered Semiconductor. He has published over 100 technical articles, holds 19 patents and received the IEEE EDS George E. Smith Award.
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GaN Device Modeling for Power and RF Applications with Industry Standard ASM-HEMT Compact Model

Prof Sourabh Khandelwal, Macquarie University, Australia

ASM-HEMT is one of the industry’s standard compact models for GaN devices, in RF and in power. Professor Khandelwal goes through its core formulations and the device effects it captures. Then come ASM-HEMT models developed for commercial use in both areas, and what’s new in the model.
The GaN HEMT model ASM-HEMT and the ESD diode model ASM-ESD are both industry standards, and he is lead author of each. Associate Professor at Macquarie University, with more than 100 papers and three books on device modeling and circuit simulation.
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Advanced Parasitics Analysis Demonstration with Viso

Ayoub HAGROU, Analog Design Engineer, STMicroelectronics

Ayoub Hagrou of STMicroelectronics takes Viso through a real circuit design. Because Viso looks only at the RC parasitics, you get to the interconnects that hurt circuit behavior quickly. Along the way come timing estimates and a side-by-side comparison of netlists from different extractions.
Designs analog circuits for STM32 general-purpose microcontrollers in STMicroelectronics’ MDG division.

Products: Viso

Watch the recording

Themes at SURGE Taiwan/Singapore 2023

Power Devices

Wide-bandgap devices for EVs and AI data centers, GaN power simulation at FBH, SiC interface traps at IME and ASM-HEMT modeling

TCAD

The Victory update, TCAD at Kepler Computing and HFC-V trap simulation on SiC

Logic and Memory

Dynamic flash and floating body memory from Unisantis, and Kepler Computing’s beyond-CMOS memory work

Advanced Packaging

Layout automation for heterogeneous integration, from National Taiwan University

Analog and Custom IC

Viso parasitic analysis, run by an STMicroelectronics designer

Related

SURGE

What SURGE is, plus every regional edition from 2022 to 2026

SURGE 2026

The most recent cycle, held online in 2026 from February 24 to March 19

SURGE 2023, USA

October 26, 2023 · Virtual event

SURGE 2023, Korea

November 16, 2023 · Virtual event

SURGE 2023, EMEA

November 21, 2023 · Virtual event

SURGE 2023, Japan

November 28, 2023 · Live event

SURGE 2023, China

December 8, 2023 · Virtual event

Events

The conference schedule for the months ahead

Webinars

Silvaco webinar recordings, including one on predicting I-V curves from process geometry