SURGE Virtual Event North America 2023

Concluded event

SURGE Virtual Event North America 2023

North America · Thursday, October 26, 2023 · Virtual event

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At a glance

October 26, 2023

Date

North America

Region

Virtual

Format

19

Sessions in 3 tracks

About this event

SURGE North America 2023 opened the 2023 cycle on October 26: the first of six regional editions, all but one held online. Three of its 19 talks came from STMicroelectronics. Micron, Tower Semiconductor, Kepler Computing and Aril sent speakers as well, and so did CEA-Leti, the Ferdinand-Braun-Institut, Purdue and TU Wien.

SURGE is Silvaco’s users event. This edition’s TCAD track leaned toward two subjects: four talks on memory devices, and three on GaN and SiC power devices.

Tracks

  • General Session
  • TCAD Track
  • EDA and IP Track

Agenda

Each of the 19 SURGE North America 2023 sessions has a recording you can download
from Silvaco’s support site. The download sits behind a support login. No login? Register first,
with an email address on a company, university or government domain.

General Session

Welcome and Introduction

Dr. Babak Taheri – CEO and Board Member – Silvaco, Inc.

Silvaco hired him in October 2018 as chief technology officer and EVP of Products, and he became CEO in August 2019. He has held that role since, apart from September to November 2021, and also sits on the board. Earlier he was CEO and president of the advisory firm Integrated Biosensing Technologies. UC Davis awarded his PhD in biomedical engineering, and he leads its electrical engineering department’s advisory board as chair.
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Machine Learning: A New Revolution for EDA

Patrick Groeneveld, Ph.D.

Getting from a functional description to a mask pattern takes a long chain of algorithms. Some are numerical solvers. Others are heuristics kept because they work. Each one carries parameters tuned by hand, like the relative costs that trade area against speed. Some recent tools let machine learning find a design-specific parameter set, by running the flow over and over and reading the gradients out of the PPA results. Research now aims at tools that are ML-driven at the core, in placement and in routing. Dr. Groeneveld maps where ML in EDA stands and what it could change over the next ten years. rnment email.
A lecturer in Stanford’s EE department, with a career that runs through Cerebras, Synopsys, Cadence and Magma. As Magma’s Chief Technologist he helped build its RTL-to-GDS2 synthesis product, and he once held a full professorship in electrical engineering at Eindhoven. He is finance chair on the Design Automation Conference’s executive committee. MSc and PhD from Delft University of Technology.
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TCAD Models as “Digital Twins" to Simulate and Optimize Semiconductor Manufacturing Processes

Patrick Groeneveld, Ph.D.

TCAD models how a device is made and how it runs, and it has become essential to deploying new semiconductor technology. Its models have become accurate enough to serve as digital twins of the manufacturing process itself. That opens two uses. Before production, you develop the technology virtually, run fewer physical experiments and reach yield sooner. During production, the same twin tunes fab processes, tracks variation and flags malfunctions. Dr. Camposano shows TCAD examples that work this way.
Silvaco’s CTO since February 2022. He spent 1994 to 2007 at Synopsys, in roles up to CTO. Later he led Nimbic, then Sage Design Automation, as CEO until Mentor Graphics and Applied Materials acquired them. He teaches EDA and machine-learning hardware at Stanford and has been an IEEE Fellow since 1999.
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TCAD Track

TCAD Simulation Update

Dr. Eric Guichard, SVP and GM of TCAD Business Unit, Silvaco, Inc.

A status report on Silvaco’s Victory TCAD simulators from the executive who runs TCAD. It covers the products themselves, the part TCAD plays whenever a new device family is developed, and where TCAD development is heading.
At Silvaco since 1995, when he started at its French subsidiary, Silvaco SA, in roles that included applications engineering. He became VP of Applications in 2008 and has run Silvaco’s TCAD work since November 2012. Grenoble INP awarded both his M.S. in materials science and his PhD in semiconductor physics.

Products: TCAD

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Impact of Surface Defect Dot on Short Circuit Phenomena

Salvatore Cascino, SiC R&D Engineer, STMicroelectronics

Switching can push a power device into abnormal overload, and some applications specify how much abuse the device must survive, through short-circuit and UIS tests. Mixed-mode circuit simulation reproduces these events. Tune its parameters against experiment and it predicts electrothermal behavior through the dynamic phase. STMicroelectronics used Silvaco TCAD to test what one defect in the active area does under short circuit. The defect dot sat in three places: the flat body/drain interface, the SiC/oxide interface along the channel, and the curved body/drain interface. A sensitivity study on its position rounds out the work.
He works on silicon carbide device technology in STMicroelectronics’ R&D group in Catania, after earlier work on sensing and RF devices. Before ST he did nuclear fusion research at ENEA in Frascati and with the RFX project in Padua. Physics degree from the University of Palermo.

Products: TCAD

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Study of Magnesium Activation Effect on Pinch-Off Voltage of Normally-Off p-GaN HEMTs for Power Applications

Giovanni Giorgino, GaN Device Engineer for ADG R&D Power & Discretes, STMicroelectronics

How much of the magnesium in a p-GaN gate actually activates shapes the off-state of a normally-off p-GaN/AlGaN/GaN HEMT. The study starts in TCAD, comparing Mg doping profiles through their band diagrams. Capacitance–voltage measurements then reveal the p-GaN’s net acceptor concentration. Devices with a magnesium-free GaN gate are set against devices activated by a reference anneal, and against a third group with improved activation. That last group gains on several parameters, in the off-state and the on-state alike.
A GaN device engineer in STMicroelectronics’ Catania R&D department since 2020, he develops, characterizes and models p-GaN gate power devices. His master’s in electronic engineering is from the Polytechnic University of Turin.
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Silvaco Simulation Tools Assisting GaN-based Power Devices Design and Development

Dr. Eldad Bahat-Treidel, Senior Scientist, Ferdinand-Braun-Institut

After two decades of research, lateral GaN power devices are close to commercial maturity for switching up to the 650 V class. They still fall short of the material’s theoretical limit on RDS_ON × A against breakdown voltage. Blocking strength trades against dispersion, and GaN on silicon caps vertical blocking. FBH is working two ways around that. Vertical GaN transistors take less wafer area than lateral HFETs, which cuts RDS_ON × A by an order of magnitude. Strain-free homoepitaxy also allows thick, lightly doped drift layers that block more than 1 kV. Lateral HFETs on an AlN buffer confine the channel behind a large conduction band offset, for stronger blocking and less dispersion.

FBH’s labs use Silvaco simulation to design these devices, predict their behavior and make sense of the measurements. The talk compares simulated conductance of GaN fin MISFETs with experiment as geometry and epitaxial layers change. It shows edge terminations for vertical devices engineered with avalanche models, and traces the dynamic on-resistance of AlN/GaN HFETs to trapping and de-trapping.

At FBH in Berlin since 2006, first on GaN switching transistors for high-voltage power electronics and, since 2014, on new devices such as vertical GaN transistors. He started out in photolithography, at Intel from 1996 and Tower Semiconductor from 2004. PhD in electrical engineering from TU Berlin.
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Going Beyond CMOS in Memories

Debo Olaosebikan Ph.D., Co-Founder and CEO, Kepler Computing

Why Kepler Computing exists, and what it’s doing to take memory design beyond CMOS. Debo Olaosebikan also shows how his team simulates those new memories in Silvaco TCAD.
Before co-founding Kepler Computing, he co-founded Gigster and served as its CTO. During his physics PhD candidacy at Cornell he led the university’s work toward an electric silicon laser, and he spent time on spintronics research at IBM Almaden. He is based in San Francisco and invests in and advises startups.

Products: TCAD

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Transport at the Nanoscale for CMOS and RRAM Applications

François Triozon, Research Scientist, CEA-Leti

Advanced CMOS and RRAM both need electron transport simulated accurately at the nanoscale. François Triozon reviews how far quantum transport simulation has come lately, and what it adds to device optimization. With 3D simulation in the NEGF (Non-Equilibrium Green’s Functions) formalism, you can pin down access resistance in tri-gate CMOS devices. The same approach now estimates contact resistance where the channel is a 2D material. RRAM is harder. For OxRAM and tunnel junctions, linking ab initio simulation to quantum transport still leaves gaps in the picture of how the device operates.
A permanent researcher at CEA-Leti in Grenoble since 2005, he simulates electron transport in nanodevices with semi-classical and quantum methods, from ab initio scale up to full devices. His work spans carbon nanotubes, 2D materials, silicon CMOS, GaN power devices, ferroelectrics and OxRAM. PhD from Université Grenoble Alpes, 2002.
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Numerical Simulations of Spintronic Magnetoresistive Memories

Nils Jørstad, PhD Researcher, TU Wien

MRAM is fast, durable and nonvolatile, which makes it a strong candidate to replace charge-based memory. Several designs switch its logical state with spin-polarized currents. Engineering problems still hold back wider adoption, and solving them takes simulation flexible enough to model how an MRAM cell really operates. Nils Jørstad presents recent results from a finite element approach that simulates charge, spin and magnetization dynamics together.
A PhD researcher since 2021 at TU Wien’s Christian Doppler Laboratory for Nonvolatile Magnetoresistive Memory and Logic, where he builds spin and magnetization dynamics into MRAM device simulation. He holds a master’s in physics, specializing in computational physics, from NTNU in Norway.
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Advanced Modeling Solutions for Development and Manufacturing of Memory Technologies

Sumeet Pandey, Distinguished Member of Technical Staff, Micron Technology

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25 Years of Quantum Transport Tool Development Resulting in a Global Impact

Gerhard Klimeck, Deputy CIO, Associate VP of Academic Research, Purdue University

Quantum transport modelers have argued over theory and prototype code for 30 years. The early test devices, 2D electron gases and room-temperature resonant tunneling diodes, date from the 1980s and 1990s, and today’s transistors have shrunk to those same critical sizes. Industry now needs predictive, quantitative models for devices near the few-nanometer limit. Gerhard Klimeck explains why it settled on the Non-Equilibrium Green Function method with an atomistic tight-binding basis. His group’s NEMO5 implementation runs at Intel, and Silvaco sells a commercial version. Through nanoHUB and chipshub, NEMO versions reach students and researchers as simple apps for exploring concepts and running detailed analysis.
He holds a chaired professorship in Purdue’s electrical and computer engineering school. He is also Purdue’s Deputy CIO and directs its Network for Computational Nanotechnology. He helped create nanoHUB.org, used by more than 2 million people a year, and co-invented a single-atom transistor. He has published more than 525 scientific articles and is a fellow of IEEE, APS, IOP and AAAS.
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Simulation of 2D-TMDs-channel FETs with Atomistic Precision

Dr. Phillipe Blaise, Silvaco, Inc.

Could transistors with 2D channels take over from silicon? Once a FET channel is only a few atomic layers thick, only an atomistic model can answer that. Dr. Blaise shows Victory Atomistic applying quantum mechanics to the question, as support for prototyping a 2D transistor inside a professional TCAD environment.
A senior application engineer for atomistic simulation in Silvaco’s TCAD team. He spent the previous 15 years at CEA-Leti simulating new memory devices and transistors atom by atom, and served on the IEEE IEDM Modeling and Simulation Committee. He has more than 50 journal papers and five patents, and a PhD in solid-state physics from Université Grenoble Alpes.

Products: Victory Atomistic

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EDA and IP Track

Analog Custom Design and IP Update

Dan Fitzpatrick, VP and GM of EDA Business Unit, Silvaco, Inc.

Dan Fitzpatrick lists the new features and functions in Silvaco’s analog custom design portfolio, then turns to the plans for Silvaco’s EDA solutions.
He runs development of Silvaco’s EDA tools, everything from analog custom design and verification to circuit simulation, SPICE modeling, standard cell layout and characterization, and IP management. He joined in 2021 to lead the IP management, cell layout and characterization lines. University of Florida MSEE, University of Central Florida MBA.

Products: Analog and Custom IC

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Power Device Modeling for SPICE

Bogdan Tudor, Silvaco, Inc.

Si, GaN and SiC power devices each bring their own particularities to SPICE modeling. Bogdan Tudor weighs compact models against macromodels as ways to capture them. Power FETs take the longest stretch, on two problems: bias-dependent capacitances, and tuning the model to dynamic characteristics. He closes with what Silvaco’s modeling team has learned about parasitic elements and model accuracy in power devices.
As head of device characterization at Silvaco, he runs the teams behind Utmost and Silvaco’s modeling services. More than 20 years on model development and characterization software.
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Silvaco and Tower Collaboration in Design Kit and Standard Cell Library Development and QA

Ofer Tamir, Managing Director, CAD, Design Enablement and Support, Tower Semiconductor

Silvaco is Tower Semiconductor’s main standard cell library provider, across all of Tower’s technologies. The newest libraries serve a 65nm advanced power management process, with advanced characterization and MTBF calculation included. On the analog side, Tower supports and qualifies its iPDK and SPICE models in Silvaco’s design flow, using Expert, Gateway, SmartLVS and SmartDRC.
He joined Tower in 2001 to direct its design enablement and CAD work. He is responsible for Tower’s design kit development, worldwide design support, CAD teams and EDA relations, and presents at conferences such as DAC. More than 30 years in EDA and CAD, including National Semiconductor (now TI) and DSPG.

Products: Expert, Gateway, SmartDRC/LVS, Standard Cell

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A High Speed, Reliable, Low Voltage SRAM for Efficient Compute

Sinan Doluca, VP of Technology, Aril, Inc.

Efficiency comes first, whether the target is a battery-powered device or an AI/ML accelerator in the cloud. Running logic and SRAM at one shared voltage, with dynamic voltage and frequency scaling, gets the most from both. The SRAM macros often set the limit, on voltage range, speed and reliability. Aril’s SRAM, optimized on an advanced CMOS process, targets fast, reliable operation from 0.45 V to 0.8 V and above. Pair it with an efficient microarchitecture and tuned physical design, and the aim is the most performance per watt, whether the engine runs compute, graphics or AI/ML work.
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Designing High-Performance I/O for Cryogenic Applications with Silvaco Analog Custom Design Platform

Ahmad S. Mazumder / Shaikh Shams, Silvaco, Inc.

At 4 K (−269°C), transistors stop behaving the way they do across the usual −55°C to 125°C range, so models built for that range don’t apply. Silvaco’s Analog and Interface IP team still delivered a fully functional 2 Gbps LVDS I/O for that temperature. Silvaco’s modeling team built model files at 4 K. The IP team then designed and laid out the PHY and produced its collateral and views, all in Silvaco EDA tools. The PHY:

  • A transmitter, a receiver and an accessory block
  • 3.5 mA transmitter drive into a 100 Ω load, independent of PVT
  • 100 Ω termination between the receiver’s PAD+ and PAD− terminals, also independent of PVT
  • Programmable equalization for board, signal-integrity (SI) and power-integrity (PI) compliance
Ahmad S. Mazumder has led development and customer support for Silvaco’s analog and interface IP as a Director of Engineering since 2019. Intel, Broadcom and C-Cube Microsystems account for most of the 28 years he spent on DDR, high-speed SerDes, interface, ESD and reliability work before that. Shaikh A Shams joined the same IP team as a Staff Engineer in 2020. His previous 22 years, split across Intel, GlobalFoundries and Dialog Semiconductor, went into AMS design and verification, voltage regulators, interfaces and high-speed SerDes.

Products: Analog and Custom IC

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Advanced Parasitics Analysis Demonstration with Viso

Ayoub HAGROU, Analog Design Engineer, STMicroelectronics

Viso is built around the parasitics alone. Working on the extracted RC network itself, it analyzes interconnect quickly and points to the problem areas, which matters because those networks can decide how a circuit behaves. It also estimates timing and compares extracted netlists accurately. The demonstration uses a real-world circuit design.
An analog design engineer on STM32 general-purpose microcontroller products in STMicroelectronics’ MDG division.
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Themes at SURGE North America 2023

Power Devices

SiC short-circuit defects and p-GaN gate activation at STMicroelectronics, vertical and lateral GaN at FBH, and SPICE models for power FETs

Logic and Memory

Memory beyond CMOS at Kepler, RRAM transport at CEA-Leti, MRAM at TU Wien, Micron’s memory modeling and Aril’s low-voltage SRAM

TCAD

The Victory update, TCAD models as manufacturing digital twins, and atomistic simulation of 2D-channel FETs

Analog and Custom IC

Tower’s design kit flow in Expert, Gateway and SmartDRC/LVS, a 4 K LVDS I/O, and Viso on parasitics

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Events

Tower Semiconductor's TGS USA symposium, November 17, 2026, is among the next stops

Webinars

Next session: SPICE model extraction from TCAD data in Utmost IV