SURGE Virtual Event China 2023

Concluded event

SURGE Virtual Event China 2023

2023年SURGE中国站线上大会

China · Friday, December 8, 2023 · Virtual event

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At a glance

December 8, 2023

Date

China

Region

Virtual

Format

20

Sessions in 3 tracks

About this event

Silvaco held SURGE China 2023 online on Friday, December 8. It was the last of six regional editions that year, which together brought in upward of 1,000 users and prospects.

SURGE gives Silvaco’s users a regular forum to trade TCAD, EDA and IP experience. This edition also took in advanced semiconductor design and display panels. Nine talks were Silvaco’s own. The other 11 came from companies and universities, among them Micron, Tower Semiconductor, Kepler Computing, Stanford and Purdue. STMicroelectronics alone sent three speakers.

Date

  • General session · 主会场
  • TCAD · TCAD 分会场
  • EDA and IP · EDA和IP分会场

Agenda

The recordings from SURGE China 2023 download as MP4 files from Silvaco’s support site.
Silvaco asks you to sign in first, or to register with a corporate, university or government email.

主会场

致欢迎辞

赵友来，中国区总经理，Silvaco

Master’s degree from Fudan University, with more than 20 years in EDA software and semiconductor IP cores.

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公司最新进展

Babak Taheri 博士，CEO及董事会成员，Silvaco

Has run Silvaco as CEO, and sat on its board, since August 2019, except for a short gap in autumn 2021. His first Silvaco role, from October 2018, was CTO and executive VP of products. Before that he was CEO and president of the consultancy Integrated Biosensing Technologies. He has also advised the MEMS World Summit, Novasentis and the UC Davis electrical engineering department. BS in engineering from San Francisco State, MS in electrical engineering from San José State, PhD in biomedical engineering from UC Davis.

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机器学习：EDA的新革命

Patrick Groeneveld 博士，斯坦福大学

An EDA flow turns a functional description of a circuit into mask patterns through a long chain of algorithms. Some are numerical solvers, others heuristics that have proved themselves. Nearly all carry parameters engineers still tune by hand, like the cost weights that trade area against speed. Machine learning changes that. Run the flow many times, read the gradients in the PPA data, and the tool settles on the right parameters for your design, fast. Dr. Groeneveld has spent recent years on ML-driven EDA tools and place-and-route strategies. He reports where the field stands and what the next ten years hold.
Lecturer in electrical engineering at Stanford and finance chair of the DAC executive committee. He has worked at Magma, Cadence, Synopsys and Cerebras, and as Magma’s CTO he developed its RTL-to-GDS2 synthesis product. He was also a full professor of electrical engineering at Eindhoven University. MS and PhD from Delft University of Technology.
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半导体制造的“数字孪生”：用TCAD模型进行工艺仿真和优化

Raul Camposano 博士，CTO，Silvaco，IEEE Fellow

TCAD already plays a key part in developing new processes, simulating each fabrication step and the device’s electrical behavior. Now the models are accurate enough to act as a digital twin of the manufacturing flow itself. That lets you develop a technology virtually, with fewer physical experiments and a shorter road to volume. Inside a running fab, the same twin can tune the process, watch for drift and flag faults. Dr. Camposano sets out the idea and walks through TCAD examples that can serve as a twin.
Silvaco’s CTO since February 2022. He has been a partner at the Silicon Catalyst incubator since 2015 and a Stanford lecturer on EDA and machine-learning hardware since 2018. He previously advised Applied Materials, and he ran Sage Design Automation as CEO until Applied Materials acquired it in 2020. From 2010 to 2014 he was CTO, SVP and general manager at Synopsys. Before that he was a professor of computer science at Paderborn University and a researcher at IBM’s T.J. Watson Research Center. IEEE Fellow since 1999. BS and MS in electrical engineering from the University of Chile; PhD in computer science from Karlsruhe.

Products: TCAD

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TCAD 分会场

Silvaco TCAD仿真最新进展

Eric Guichard 博士，公司副总裁及TCAD事业部总经理，Silvaco

Dr. Guichard opens with the latest Victory TCAD releases. He then explains why the devices coming next will lean on TCAD, and closes with what’s planned for the tools themselves.
Responsible for Silvaco TCAD from R&D through field deployment. He joined Silvaco in 1995 and has led Silvaco France and worldwide TCAD field operations. Before that he was a senior SOI engineer at LETI and at Thomson’s military and aerospace business, specializing in transistor and circuit aging. Grenoble INP awarded both his degrees: an MS in materials science and a doctorate in semiconductor physics.

Products: TCAD

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表面缺陷点对短路现象的影响

Salvatore Cascino，SiC研发工程师，STMicroelectronics

Some applications set robustness specs for switching overloads, with short-circuit and UIS tests among them. Mixed-mode circuit simulation can reproduce those events. Once its parameters are tuned against measurements, it predicts the device’s electro-thermal behavior through the transient. ST’s case study uses Silvaco TCAD to ask how a surface defect in the active area changes short-circuit behavior, and how much its position matters.
Physics graduate of the University of Palermo. He worked on nuclear fusion research at ENEA Frascati (the FTU project) and in Padua (RFX). He is now in STMicroelectronics R&D in Catania, developing SiC device technology. His earlier work covered sensing applications and RF devices.

Products: TCAD

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GaN功率应用市场和器件技术

邱绍谚 博士，氮化镓电力电子部研发总监，华灿光电

GaN is moving into power applications that SiC MOSFETs and silicon IGBTs have held. The talk sizes up that market and weighs the emerging fourth-generation materials, then turns to device physics. Silvaco TCAD results show material defects shifting leakage current and breakdown voltage, while defect recombination slows switching and weakens stability. Today’s commercial GaN power devices are lateral epitaxial structures, so TCAD is used here to tackle current collapse in them. The talk closes on the advantages of vertical GaN and where it’s heading.
More than 15 years across academic research, semiconductor manufacturing and design companies. He graduated from National Taiwan Ocean University’s electrical engineering institute in 2009. Since then he has worked on third-generation semiconductor epitaxy and process, and on lateral and vertical GaN power device structures. He has published more than 50 papers on compound semiconductors. Postdoctoral researcher at Tsing Hua University in Taiwan; selected for Zhejiang Province’s Thousand Talents program.

Products: TCAD

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常关型p-GaN HEMTs中，Mg激活对截止电压的影响的研究

Giovanni Giorgino，ADG GaN功率和分立器件研发工程师，STMicroelectronics

How magnesium doping, and how much of it is electrically activated, sets the off-state of a p-GaN/AlGaN/GaN HEMT. TCAD first compares Mg doping profiles through their band diagrams. Capacitance-voltage measurements then pin down the net acceptor concentration in the p-GaN. The comparison runs from an undoped GaN gate to a p-GaN gate activated by the reference anneal. Then comes a device with improved activation, which gains on several on-state and off-state parameters. For normally-off GaN HEMTs, the activation step carries much of the overall performance.
MS in electronic engineering from Politecnico di Torino, 2020. Since then he has been a GaN device engineer in STMicroelectronics R&D, developing, characterizing and modeling p-GaN gate devices for power applications. Background in semiconductor physics, analog circuits and power electronics.
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Silvaco TCAD仿真在先进逻辑与存储器件的应用实践

李茂，先进CMOS TCAD总监，Silvaco中国

Every shrink since the 1947 point-contact transistor has changed which device parameters matter, and by how much. TCAD process and device simulation keeps that in view through design, analysis and process development. This talk reviews what Silvaco TCAD has added for advanced logic and memory in recent years, with worked examples in logic CMOS, DRAM and 3D NAND.
MS from KU Leuven, where he was a research assistant at imec on early 2D-materials work, fabricating and characterizing MoS2 transistors. From 2017 he worked on TCAD process and device simulation at SMIC R&D and at HiSilicon, mainly on advanced logic devices and DTCO. At Silvaco he leads the application engineering team for the foundry business.

Products: TCAD

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用于存储技术开发和制造的先进建模解决方案

Sumeet Pandey，高级技术经理，Micron

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超越CMOS的存储器设计

Debo Olaosebikan，联合创始人及CEO，Kepler Computing

Quantum transport modeling has been studied for three decades. In the 1980s and ’90s, the test devices were two-dimensional electron gases and room-temperature resonant tunneling diodes. Those early devices are now well understood, down to how their critical dimensions play out in nanotransistors. Taking devices to their final nanometers needs models that predict quantitatively. Prof. Klimeck explains why industry settled on atomistic tight-binding with non-equilibrium Green’s functions (NEGF), and on NEMO5, which Silvaco commercialized and Intel adopted. Through nanoHUB and chipshub, versions of NEMO reach students and researchers as easy-to-run apps.
Professor of electrical and computer engineering at Purdue. He is also associate CIO and associate VP for academic IT there, and directs both the Network for Computational Nanotechnology and the Center for Predictive Materials and Devices. He helped create nanoHUB.org, which serves more than 2 million users a year. Fellow of IOP, APS, IEEE, AAAS and the Humboldt Foundation, with more than 525 publications. He co-invented the single-atom transistor, and Intel has used NEMO5, developed by his group, for nanotransistor design since 2015. The nanoHUB team won an R&D 100 award for opening up access to simulation and data.

Products: TCAD

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25年来量子输运工具的开发成果及在全球产生的影响

Gerhard Klimeck 教授，nanoHUB主任，普渡大学，IOP/APS/IEEE Fellow

Quantum transport modeling has been studied for three decades. In the 1980s and ’90s, the test devices were two-dimensional electron gases and room-temperature resonant tunneling diodes. Those early devices are now well understood, down to how their critical dimensions play out in nanotransistors. Taking devices to their final nanometers needs models that predict quantitatively. Prof. Klimeck explains why industry settled on atomistic tight-binding with non-equilibrium Green’s functions (NEGF), and on NEMO5, which Silvaco commercialized and Intel adopted. Through nanoHUB and chipshub, versions of NEMO reach students and researchers as easy-to-run apps.
Professor of electrical and computer engineering at Purdue. He is also associate CIO and associate VP for academic IT there, and directs both the Network for Computational Nanotechnology and the Center for Predictive Materials and Devices. He helped create nanoHUB.org, which serves more than 2 million users a year. Fellow of IOP, APS, IEEE, AAAS and the Humboldt Foundation, with more than 525 publications. He co-invented the single-atom transistor, and Intel has used NEMO5, developed by his group, for nanotransistor design since 2015. The nanoHUB team won an R&D 100 award for opening up access to simulation and data.
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EDA和IP分会场

Silvaco EDA与IP最新进展

Dan Fitzpatrick，公司副总裁及EDA事业部总经理，Silvaco

Dan Fitzpatrick’s update spans two product lines, the analog custom design tools and Silvaco IP: what each has gained, and where each goes from here.
Responsible for developing all of Silvaco’s EDA tools: analog custom design and verification, circuit simulation and SPICE modeling, standard cell layout generation and characterization, and IP management. He joined in 2021 to lead the IP management and standard cell lines. Before that he spent years in EDA software development and product management, at companies from startups to the Fortune 500. His MS in electrical engineering is from the University of Florida, his MBA from the University of Central Florida.

Products: Analog and Custom IC, Design IP

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Silvaco 半导体仿真平台助力功率器件开发与仿真

常志强，TCAD技术总监，Silvaco中国

Wide-bandgap power devices are showing up in more products, and development teams want quicker ways to get them designed. This session walks through the Silvaco tool chain for power device work. It runs from layout and physical verification, through process and device simulation, to SPICE model extraction and circuit simulation, and shows what each step contributes.
He has long handled Silvaco TCAD technical outreach and customer support in China. He helps customers build their own TCAD simulation capability for process and device work. BS from Nanjing University, MS from Fudan University.
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Tower携手Silvaco：设计工具包和标准单元库的开发与验证

Ofer Tamir，CAD、设计实现与支持总监，Tower Semiconductor

Tower’s standard cell libraries come mainly from Silvaco, on every Tower process node. The latest set targets Tower’s 65nm power management process and adds advanced characterization and MTBF calculation. Tower, an analog foundry, also supports and validates its iPDKs and SPICE models with Silvaco’s analog design flow. Expert, Gateway, SmartLVS and SmartDRC are all in the loop.
He joined Tower in 2001 as director of design enablement and CAD. He is responsible for all design kit development and for CAD and design support worldwide. More than 30 years in EDA and CAD, at National Semiconductor (now TI), DSPG and Tower. He also manages Tower’s EDA industry relationships and speaks at DAC and technology forums.

Products: Expert, Gateway, SmartDRC/LVS, Standard Cell

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用于高效计算的高速、可靠、低电压SRAM

Sinan Doluca，技术副总裁，Aril

From battery-powered devices to AI/ML accelerators in the cloud, efficiency is the constraint. Running logic and SRAM on one supply, with dynamic voltage and frequency scaling, gets the most from both. That holds until the SRAM macros hit their voltage, speed and reliability limits. The SRAM technology in this talk, built on optimized CMOS, targets fast, reliable operation from 0.45 V to 0.8 V and above. Paired with an efficient microarchitecture and tuned physical design, it pushes performance per watt in compute, graphics and AI/ML engines.
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利用Silvaco ACD平台进行超低温应用的高性能I/O设计

Ahmad S. Mazumder和Shaikh A Shams，Silvaco

Silvaco’s analog and interface IP team designed and delivered a fully working 2 Gbps LVDS I/O that runs at 4 K (−269°C). Devices behave differently there than across the standard −55°C to 125°C range, so the modeling team first built model files for that temperature. The IP team then designed and laid out the PHY, and produced its views, in Silvaco EDA tools. The PHY pairs a transmitter and a receiver with auxiliary blocks. It drives 3.5 mA into a 100 Ω load, with a 100 Ω termination between the receiver’s PAD+ and PAD−, both independent of PVT. Programmable transistors trim it for board-level, signal-integrity and power-integrity compliance.
Ahmad S. Mazumder. Leads engineering for Silvaco’s analog and interface IP, both development and customer support, since joining in 2019. Before Silvaco came 28 years at SoC companies, C-Cube Microsystems, Broadcom and Intel among them, on DDR and high-speed SerDes, interfaces, ESD, and quality and reliability. MS in VLSI semiconductor design, City University of New York; BS in electrical and electronic engineering, Bangladesh University of Engineering and Technology. Shaikh A Shams. Designs analog and interface IP at Silvaco, where he has been a senior engineer since 2020. Before that came 22 years at Dialog Semiconductor, GlobalFoundries and Intel, on high-speed SerDes, interfaces and voltage regulators, plus AMS design and verification. He holds an MS in electrical and computer engineering (University of Arizona).

Products: Analog and Custom IC, LVDS

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Viso：先进的寄生参数分析解决方案

Ayoub Hagrou，模拟设计工程师，STMicroelectronics

Compare extracted netlists accurately, spot the parasitics hurting a net and estimate its timing, all from one interface. That’s the job Viso does, working on the RC network where circuit behavior is often decided. Ayoub Hagrou of STMicroelectronics runs it on real circuit designs.
Analog design engineer on STM32 general-purpose microcontrollers in STMicroelectronics’ MDG division.

Products: Viso

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显示DTCO——从TCAD到系统仿真

郭小军 教授，上海交通大学

AMOLED is thin enough to win phones and wearables. But as OLED efficiency and pixel resolution rise, peak pixel current falls, and the TFTs spend more of their time at low gray levels. Fine control and uniformity get harder there. Image quality turns sensitive to the device itself and to outside factors: ambient light, and charge trapped in the substrate or at interfaces. The talk presents a display DTCO method that couples TCAD with system simulation. It traces how material and device properties reach the image and checks the outside factors. It also gives you a way to test drive schemes and image processing against non-ideal display behavior.

Tenured professor and vice dean of the School of Electronic Information and Electrical Engineering at Shanghai Jiao Tong University. He joined in 2009 after flexible display R&D at Plastic Logic (now FlexEnable). His research covers transistors, displays and sensors, hybrid device-circuit design, heterogeneous integration and new manufacturing methods, with more than 100 papers as first or corresponding author. He serves on the IEEE EDS Board of Governors and the IEEE TED and J-EDS editorial boards, and is deputy secretary-general of SID-China. His honors include SID Presidential Citations in 2018 and 2020 and an IEEE EDS Distinguished Lecturer appointment. BS from Jilin University (2002); PhD in electronic engineering from the University of Surrey (2007).

 
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显示技术的4端TFT紧凑型模型及动态仿真方法

Won-Seok Lee，高级应用工程师，Silvaco韩国

Senior application engineer at Silvaco Korea, with more than 25 years in modeling and device simulation. He supports EDA customers across CMOS, display and power/RF devices, and developed a high-accuracy dynamic hysteresis model for AMOLED circuit simulation.
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What SURGE China 2023 covered

Product family

TCAD

The Victory TCAD update, fab digital twins, and device studies from ST, Kepler Computing and 华灿光电

Solution

Power Devices

SiC short-circuit robustness, p-GaN HEMT threshold voltage, and where GaN power is heading

Solution

Logic and Memory

Logic CMOS, DRAM and 3D NAND simulation, Micron’s memory modeling and memory beyond CMOS

Solution

Display

Display DTCO from TCAD to system level, and four-terminal TFT compact models

Product family

Analog and Custom IC

Viso parasitic analysis, Tower’s design kits and a 4 K LVDS I/O

Related

SURGE

The user conference itself, and its archive back to 2022

SURGE 2026

The latest cycle, with a keynote from Micron's Gurtej Sandhu

SURGE 2023, USA

October 26, 2023 · Virtual event

SURGE 2023, Korea

November 16, 2023 · Virtual event

SURGE 2023, EMEA

November 21, 2023 · Virtual event

SURGE 2023,
Taiwan/Singapore

November 23, 2023 · Virtual event

SURGE 2023, Japan

November 28, 2023 · Live event

Events

The year's trade-show dates, IEDM and TSMC's forums among them

Webinars

Silvaco's webinar series; Utmost IV SPICE model extraction is next