MIPI M-PHY
MIPI M-PHY IP: high-speed serial physical layer
If your SoC needs UFS flash storage or a chip-to-chip link, Silvaco’s MIPI M-PHY IP gives you an M-PHY v4.1 physical layer running HS-G1 through HS-G4, with a top rate of 11.6 Gbps.
Available MIPI M-PHY IP, by foundry and node
Match the foundry, node and grade to your target process before anything else.
| Foundry | Product Name | Features | Part Number | Grade |
|---|---|---|---|---|
| TSMC | M-PHY HS-G4 (11.66Gbps) in TSMC 40G | Supports MIPI M-PHY, 11.66Gbps |
Grade: C = commercial, I = industrial. Building on another foundry or node? Ask about M-PHY coverage for your process
Applications
The two links M-PHY carries on your SoC.
Storage interfaces
UFS flash storage links, with MIPI UniPro support.
High-speed chip-to-chip links
Two processors on separate chips, talking over one serial link.
Mixel had M-PHY in silicon first
It did the same with D-PHY and C-PHY, each one working in silicon before a datasheet existed. The listed part is named down to its part number, so you can check it against the process your program already uses.
v4.1
spec version, backwards compatible
HS-G1 to HS-G4
high-speed gear range
11.6 Gbps
top high-speed rate
TSMC 40 nm
foundry and node of the listed part
Customer · Mixel MIPI IP (D-PHY)
November 2025
indie
indie's automotive radar processors and MMICs carry Mixel's ASIL-B D-PHY CSI-2 TX and RX IP. It shipped with a safety manual and certified automotive functional safety deliverables.
“We needed a MIPI IP provider that could support our strict automotive requirements to further our radar portfolio and enable efficient and scalable ADAS architecture solutions. Through our long-standing partnership with Mixel and their extensive automotive experience, we had full confidence in Mixel's capabilities and reliability. We are looking forward to our continued collaboration.”
Peter Gulden, EVP Radar Systems and Software, indie
Catalog · PDF
Summer 2026
PRO IP catalog
Look up M-PHY alongside the D-PHY, C-PHY and combo PHY parts, all in one PDF.
Press release
March 2026
Mixel PHYs now production-ready at Silvaco
M-PHY v4.1 launched as PRO IP next to the D-PHY and C-PHY families, with UniPro and UFS support.
Check M-PHY against your process
Send the foundry and node you’re targeting, plus the gear you need. A Silvaco IP specialist comes back to you on licensing, and on whether M-PHY is available for that process.
MIPI M-PHY IP questions
What is MIPI M-PHY?
It's the MIPI Alliance's serial physical layer for fast, low-power links, to storage and between chips. Silvaco's MIPI M-PHY IP, built by Mixel, supports v4.1 and stays backwards compatible. You get HS-G1 through HS-G4, topping out at 11.6 Gbps. The low-speed PWM gears are covered too.
Where is M-PHY used?
Two places, mainly: flash storage and chip-to-chip links. Because the IP supports JEDEC Universal Flash Storage, it fits a UFS interface on your SoC. The same dual-simplex link also handles inter-processor communication between two chips. Burst-mode operation saves power, and adjustable slew rate and amplitude help you keep EMI down.
How does M-PHY differ from D-PHY and C-PHY?
The difference starts with the wiring. M-PHY runs point to point over a pair of one-way links with 8b10b encoding. It's made for storage and chip-to-chip data. D-PHY pairs one to four data lanes with a forwarded clock, and C-PHY sends data on one to three trios. Both of those carry CSI-2 camera and DSI display traffic.
Which parts are available?
One: part number 20X313, an M-PHY HS-G4 on TSMC's 40 nm G process, offered in commercial and industrial grades. Need a different gear set, grade or configuration for your program? Tell an IP specialist what you're building and ask what else can be done.
Which foundries and nodes?
TSMC, at 40 nm in its G process, is the only foundry and node on the M-PHY list right now. If your program runs on a different process, put the foundry and node in your first message to an IP specialist. That one detail settles whether M-PHY can work for you.
What is UniPro?
UniPro is MIPI's transport protocol for linking chips, a layered stack with M-PHY underneath as the physical layer. JEDEC built Universal Flash Storage on that same pairing of UniPro over M-PHY. Silvaco's MIPI M-PHY IP supports both, so your storage and chip-to-chip ports can share the same M-PHY IP.
Related
MIPI D-PHY
One to four data lanes and a forwarded clock, for camera and display links.
MIPI C-PHY
One to three trios instead of lanes, carrying CSI-2 and DSI traffic.
MIPI
The three MIPI physical layers, D-PHY, C-PHY and M-PHY, in one family.