LVDS Serializer
LVDS serializer IP
LVDS serializer IP from Mixel, a Silvaco company, for teams whose SoC sends parallel data to a display panel over four LVDS channels, available at TSMC 40LP and UMC 40ULP.
What the LVDS serializer does on your chip
It’s the sending end of the link, from your SoC out to the panel.
Parallel in, serial out
Your SoC hands over parallel data and the serializer puts it on four LVDS data channels, with a fifth channel carrying the clock. You set the width at 7 or 10 bits per channel. The input clock can sit anywhere from 25 to 165 MHz.
Reach without the noise
Long cable run? Switch on transmit pre-emphasis and the bit error rate stays low over the extra distance. The low-swing output keeps EMI down, the PLL needs nothing off-chip, and the link meets TIA/EIA-644.
Pairs with the LVDS Deserializer
On the receiving chip, the LVDS Deserializer rebuilds your parallel data from those four channels, using the width you chose on this side. Mixel designed the two as one link.
LVDS serializer IP by foundry and node
Check your foundry first. Silvaco lists two parts, one at each foundry, and both come in
commercial, industrial and automotive grades.
| FOUNDRY | PART NAME | FEATURES |
|---|---|---|
| UMC | LVDS TX+ in UMC 40ULP | Supports LVDS, 4CH, 770Mbps, full speed loopback description |
| TSMC | LVDS TX in TSMC 40LP | Supports LVDS, 4CH, 1000Mbps |
CH counts LVDS channels, and each rate is per channel. The LVDS Deserializer handles the receiving end. If your chip also
has to transmit MIPI D-PHY, the D-PHY/LVDS Combo TX drives both. Different foundry or
process? Talk to an IP specialist.
Applications
Where the serializer’s output ends up.
Display transmit links
Pixel data from your SoC to a flat panel, the job Mixel built the serializer for.
Automotive display
In-vehicle screens, using the automotive-grade versions of either part.
Industrial panel drivers
Industrial panels with an LVDS input, driven straight from your SoC.
Proof you can check
You shouldn’t have to take a vendor’s word for the basics.
2 parts
LVDS serializers listed, one at TSMC and one at UMC
1000 Mbps
per channel on the TSMC 40LP part
TIA/EIA-644
the LVDS standard the output meets
5 Gbps
across all four channels, the throughput Mixel specifies for the design
Catalog · PDF
Summer 2026
Silvaco IP catalog
Both LVDS serializer parts with part numbers and grades, alongside the deserializer and every other interface part Silvaco lists.
Product page · mixel.com
Summer 2026
Mixel LVDS Serializer
Architecture, clock range, pre-emphasis and the full feature list, on Mixel's own page.
Ask about your process
Tell an IP specialist your foundry, node and link, and you’ll find out which of the two
LVDS serializer parts fits and what licensing involves. Ask for
the datasheet on the same call.
Questions about LVDS serializer IP
What is an LVDS serializer?
It takes a chip's parallel data and sends it out as low-voltage differential signals over a few serial channels, and the low signal swing keeps EMI down. Mixel's version runs four data channels plus a clock channel and meets TIA/EIA-644. Silvaco lists one part at each of TSMC 40LP and UMC 40ULP.
How does it pair with a deserializer?
The serializer sits on the transmitting chip and the deserializer on the receiving one. It turns the four serial channels back into the 7- or 10-bit parallel words the transmitting SoC started with. Silvaco lists one deserializer part: an LVDS RX at TSMC 40LP, 1000 Mbps per channel.
Which foundries and nodes are available?
Two: TSMC 40LP, with an LVDS TX, and UMC 40ULP, with an LVDS TX+. Each has an automotive-grade version too. Mixel builds its LVDS cores in modular blocks that tolerate process variation, so if your foundry isn't one of these, ask an IP specialist about porting.
What data rates are supported?
Per channel, up to 1000 Mbps at TSMC 40LP and up to 770 Mbps at UMC 40ULP. Mixel rates the design underneath both at 1.25 Gbps per channel, or 5 Gbps across all four. The part you license sets your ceiling.
How many lanes are supported?
Four data channels, plus a fifth for the clock. LVDS calls a lane a channel, so part listings read 4CH. On the parallel side you program 7 or 10 bits per channel and feed an input clock between 25 and 165 MHz. Data can strobe on either clock edge.
How does this differ from a MIPI D-PHY transmitter?
Both can carry display data, to different specifications. LVDS sends TIA/EIA-644 signals over data channels with their own clock channel, usually feeding a panel directly. MIPI D-PHY transmitters follow the MIPI Alliance spec, switching between high-speed and low-power modes to carry DSI or CSI-2. Want both in one PHY? That's the D-PHY/LVDS Combo TX.
Related
LVDS Deserializer
The receiving end of the link.
D-PHY/LVDS Combo TX
Transmit LVDS or MIPI D-PHY from one PHY.
D-PHY/LVDS Combo RX
Receive LVDS or MIPI D-PHY on one PHY.