Simulation Standard

Silvaco now offers the MOS31 JFET/MOSFET model originally developed by Philips [1] as part of the SmartLib product-independent model library. This model is available within SmartSpice as level 31.

Bulk CMOS is currently the dominant technology for VLSI integrated circuits but its scaling constraints pose ever greater as device geometries shrink. Thus, the search for a suitable replacement has

A. Previous articles in the Simulation Standard have highlighted the diffusion models required for accurate simulation of shallow source/drain junction formation[1] and Reverse Short Channel Effect (RSCE)[2][3]. However for complete

Q: I want to draw several long wires, with precise positioning of both ends. I am used to doing this as follows:

Maverick is a sophisticated full chip hierarchical netlist extractor [1]. It augments the existing CELEBRITY framework which includes state-of-the-art software for VLSI layout editing, hierarchical design rule checking and layout

In a previous issue of Simulation Standard for Process and Device Engineers[1] the simulation of a three stage CMOS ring oscillator using ATLAS/MixedMode was introduced. The MOSFETs used in the

There has been a significant increase in the popularity of liquid crystal displays with control circuitry being placed on to the glass (system on a panel). This has been made

ATHENA version 5.0 includes a new Binary Collision Algorithm (BCA) for accurate Monte-Carlo implant modeling down to sub-1keV energies. This new BCA code is a 3D model that takes account

A. The BSIM3_MG routine in SOI module of UTMOST III can be used to extract SOI model parameters. The SOI BSIM3_MG routine operation is similar to the one in MOS

The addition of important features in the latest version of SPAYN (1.7.3.R) makes it an even more useful and versatile statistical parameter and yield analysis tool. The list of spice