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Simulation Standard
Know how your circuit behaves across process variation before silicon tells you, with Monte Carlo-accurate results up to 30X faster.
27 years ago
Hints & Tips October 1999
A. It is likely that there may be some contact problems or defected devices during the data collection. This problem can occur when the log file is open and some
27 years ago
New Improvements in TFT Models: Amorphous (Level=35) and Poly-Silicon (Level=36) TFT
New improvements have been added to Shur models. These enhancements include a self-heating effect and a new charge conservative model.
27 years ago
BSIM3SOI Version 2.1 (FD, DD and PD) Models Released in SmartSpice
The Berkeley BSIM3SOI version 2.1 models, released in September 1999, have been implemented in SmartSpice. The three new models are selected according to LEVEL selector.
27 years ago
Hints & Tips September 1999
Q: How can I cut exactly the same hole in many layers? A: There are at least two ways to do this. (1) You may use the command Tools>>Cut by
27 years ago
Scholar: An Enhanced Multi-Platform Schematic Capture
One of the main features of modern complex CAD systems consists in the ability to support the schematic capture function that provides a user with convenient design entry. In our
27 years ago
Hints & Tips August 1999
A: Modeling of the increase in breakdown voltage at elevated temperatures requires a model to describe the temperature dependence of the impact ionization coefficients. In ATLAS there are two impact
27 years ago
High Performance ATHENA and ATLAS Simulation on PC under NT
The recent advances in PC hardware capability in terms of memory and CPU floating point performance has allowed the possibility of running realistic sized ATHENA and ATLAS problems on PCs.
27 years ago
New Thermionic Emission and Tunneling Models in ATLAS
In order to simulate heterojunction devices accurately, both the thermionic emission and tunneling mechanisms must be considered when calculating transport across hetrojunctions. Drift-diffusion descriptions of carrier mobility are incomplete at
27 years ago
Generating a Capacitance Coefficient Database for any Chip Level LPE Tool Using EXACT
EXACT is a sophisticated interconnect characterization tool integrated into the DISCOVERY framework. It is designed to build the capacitance coefficient database required by any Layout Parasitic Extraction (LPE) tool. To
27 years ago
Hints & Tips July 1999
The "Binning" routine in UTMOST III MOS module has been greatly enhanced. The bin models can be generated much faster and the routine requires less user interface.