It is common to run the process simulation for the part of a larger structure just to reduce the computation time. To account for the influence of parts of the structure outside the simulation domain, Victory Process makes assumptions about overall structure geometry.
https://silvaco.com/wp-content/uploads/2023/03/SimStd_Mar2023_Thumnail.png326250Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2023-03-07 15:27:492023-03-10 09:14:43Understanding of Geometrical Boundary Conditions in Victory Process
The utilization of thin material layers is common in modern semiconductor device fabrication. Subsequent etching steps require an accurate modeling of these thin layers. Although level-set based process TCAD simulations are capable of representing flat thin material layers with sub-grid accuracy, topographical changes during etching processes expose the low underlying grid resolution, which leads to detrimental artifacts.
https://silvaco.com/wp-content/uploads/2023/02/Q1_SS_Feb2023.png323250Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2023-02-09 11:31:092023-03-07 15:33:55Automatic Grid Refinement for Thin Material Layer Etching in Process TCAD Simulations
Silver, DeckBuild’s material database viewer, can be used to examine the default parameters in the Silvaco Material DataBase (SMDB) and to generate MATERIAL commands for Victory Process and Victory Device. Silver can be started by clicking the launch button in DeckBuild.
https://silvaco.com/wp-content/uploads/2023/01/SimStd_Jan2023_Thumnail.png327250Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2023-01-13 10:40:302023-03-08 14:44:29How to Search, View and Use Default Parameters from the Silvaco Material DataBase SMDB with DeckBuild
The GaN high electron mobility transistor (HEMT) has been commercialized as a power device with performance superior to Si devices in the voltage classes from 15 V to 900 V . Most of commercial enhancement-mode (E-mode) HEMTs comprise a planar p-GaN gate. Recently, 3-D gate stacks, such as FinFET and tri-gate structures, have been introduced to lateral GaN HEMTs. They can realize superior gate controllability and E-mode operation with a higher current on/off ratio and lower gated channel resistance .
Accuracy of Impurity Activation is essential in correctly modeling and simulating Silicon Carbide devices. For high concentrations of dopants, it is well known that less than 100% of dopants will be electrically active. To address this effect, Silvaco Victory Process models dopant activation in Silicon Carbide in 3 ways.
https://silvaco.com/wp-content/uploads/2022/10/Q3_SS_Oct2022.jpg319250Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2022-10-27 13:37:392022-12-13 15:23:01Writing an Impurity Activation Model with the Open Model Library
One of the new features in Victory Device is the ability to add user managed parameters to a log file. This can be used when sweeping parameters (manually or in a Deckbuild loop), such as doping, stress, or layer thicknesses, to add the swept parameter to a log file. To do so, simply create a USER probe (with an optional name), and set the parameter USER on the MODELS statement to some value. This parameter (and value) will be added to the log file. The available user parameters are USER1, USER2, USER3, and USER4. The following shows a DeckBuild loop (go victoryd) to simulate the effect of varying STRESS_XX on the mobility.
https://silvaco.com/wp-content/uploads/2022/09/Q3_SS_Sep2022thumbnail.png322250Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2022-09-16 14:54:102023-03-09 10:59:36User Probes and Arbitrary Parameter Sweeps in Victory Device
The FET physical dimensions continue to shrink to five nm node and below, characterized by new types of architectures with nanosheet (NS) and nanowire (NW) shapes . The present choice of material is made of Si, Ge, or SiGe alloy thanks to their high carrier concentrations. In compliment to III-V technology envisaged for a while, new 2D materials are also investigated (for example, the TMDs monolayers1). Such nanomaterials and nano-architectures require atomistic simulations for at least two crucial reasons: 1) bulk parameters like the effective masses and forbidden bandgap are no longer pertinent quantities, and 2) the wave nature of charge carriers becomes predominant for predicting transport characteristics including scattering events.
https://silvaco.com/wp-content/uploads/2022/08/Q2_SS_Aug2022_thumbnail.png321250Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2022-08-23 14:46:572023-03-09 10:44:34Quantum Transport Simulation at Atomistic Accuracy of a Nanowire FET
This work reports on the design of a high efficiency InGaN-based two junction (2J) tandem solar cell via numerical simulation, operating at high temperatures (450o C) and under 200 suns for application in a hybrid concentrating solar thermal (CST) system. To address the polarization and band-offset issues for GaN/InGaN heterojunction solar cells, band engineering techniques are employed. A simple interlayer is proposed at the hetero-interface rather than using an In composition grading layer, which is difficult to fabricate. The base absorber thickness and doping concentration have been optimized for 1J cell performance, and current matching was imposed on the series constrained 2J tandem cell design. The simulation results show that the crystalline quality (short recombination lifetime) of current nitride materials is a critical limiting factor the performance of the 2J cell design at high temperatures. The theoretical conversion efficiency of the best devices can be as high as ~21.8% at 450o C and 200X based on the assumed material parameters.
https://silvaco.com/wp-content/uploads/2022/06/Q2_SS_Jun2022_thumbnail.png330250Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2022-06-14 12:16:072023-03-09 09:59:49Simulation of the High Temperature Performance of InGaN ‘Topping’ Cells
Self-heating effect may cause over-heated damage and degradation for silicon-on-insulator (SOI) devices, so numerical counting heat generated, and distribution can optimize the radio frequency integrated circuits (RFICs) applications. Both conventional and high resistivity, trap-rich SOI substrates are fabricated to investigate self-heating effects. There are two identical n channel metal-oxide-semiconductor-field-effect transistors (nMOSFETs) placed together to share a common source and the same active silicon region. One MOSFET is biased above threshold voltage and into saturation to heat-up the active region as a heater, and another device is biased into the sub-threshold regime to track the temperature changes as a localized thermometer. Compared to bulk single crystal silicon, the trap-rich SOI substrate consists of a high-defected polysilicon layer, which has introduced between the buried oxide layer and substrate. Due to the grain boundaries, the polysilicon layer has more phonon scattering and less value of thermal conductivity. However, based on the measurement results, two types of substrates SOI devices have similar performance for temperature increased. Therefore, a Silvaco numerical simulation has been issued to analysis the heat flow distribution within the devices and dissipation solution.
https://silvaco.com/wp-content/uploads/2022/04/Q2_SS_Apr2022_thumbnail.png319250Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2022-05-03 14:10:132023-03-09 09:52:27Investigation of Self-Heating Effects in SOI MOSFETs with Silvaco Numerical Simulation
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