Simulation Standard

A great deal of recent industry attention has focused on the use of non-planar multi-gate device structures in future generation MOS devices that feature channel lengths below about 50 nm

In order to investigate the influence of ridge separation on the transverse optical modes of a double ridge edge multiple quantum well (MQW) emitting laser, we have designed a generic

The trend toward smaller MOSFET devices with thinner gate oxide and greater doping is resulting in the increased importance of quantum mechanical effects, which are observed as shifts in threshold

It is possible to now create new heterojunction and double heterojunction bipolar transistors [2] utilizing junction layers made of different heterojunction semiconductor materials. Typically a heterojunction bipolar transistor (HBT) consists

When an implant occurs there will be some level of damage to the crystal structure of the silicon. If this damage is not annealed out then any subsequent implant will

Implementation of a new ferroelectric capacitance model from Ramtron International Corporation into SmartSpice was first described in the April 2002 issue of Silvaco Simulation Standard. This model utilizes a new

Version 7.0 of the University of Florida Silicon-On-Insulator (UFSOI), released in 2002, is now available with Silvaco SmartSpice by setting LEVEL to 21. SmartSpice uses version 7 by default, but

Silvaco SmartSpice simulation results are typically stored in RAM. Since transient simulations of large circuits often exceed 1GB, a large swap-space partition is required prior to simulation. Constant disk access

One of the methods to define a Voltage Controlled Oscillator (VCO) in a SPICE simulation is to make use of a voltage-controlled voltage source (E element). A typical VCO expression

Level=36 RPI poly-Si TFT and other original TFT models do not support automatic geometry binning. The enhanced model included with SmartSpice 1.9.7.C or later now supports the selecting of a