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1 week ago

001_LNA : LNA schematic RF Simulation

Minimum Required Versions: Gateway 2.12.8.R, SmartSpiceRF 1.6.3.R Typical Low Noise Amplifier (LNA) designs utilize reasonable gain and a low noise figure to provide stability without oscillation over the useful range

1 week ago

002_mixer : RF Mixer Schematic Simulation

Minimum Required Versions: Gateway 2.12.8.R, SmartSpiceRF 1.6.3.R RF Example 2 is a mixer design ( mixer.png ). The three ports of the mixer are the Local Oscillator port (LO), the

1 week ago

003_freq_divider : RF Frequency Divider Schematic Simulation

Minimum Required Versions: Gateway 2.12.8.R, SmartSpiceRF 1.6.3.R The schematic for Example 3 ( schematic.png ) is a frequency divider design. Since the division factor is 4, the fundamental frequency is

1 week ago

001_RSFF_sim : RS Flipflop Schematic Simulation

Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R The Gateway schematic front end can capture digital circuits for netlisting in the verilog format and simulating in the Silvaco SILOS simulator. To

1 week ago

002_adpll : All Digital PLL Schematic Simulation

Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R Example 2 is an all digital PLL schematic design ( all_digital_PLL.png ). In the design browser, clickING on the parameters entry displays the

1 week ago

003_one_bit_adder : One Bit Adder Schematic Simulation

Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R Example 3 is a one bit adder verilog design. The schematic ( schematic.png ) is shown consisting of gate level primitives and one_bit_adder.v

1 week ago

004_ripple_carry_counter : Ripple Carry Counter Schematic Simulation

Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R Example 4 is a four bit ripple carry counter schematic. The top level of the design ( top_level.png ) is made from negative

1 week ago

005_vending_machine : Verilog Vending Machine Schematic Simulation

Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R Example 5 is a schematic example of a finite state machine. The example models a vending machine that outputs a newspaper based on

1 week ago

006_drink_machine : Verilog Drink Machine Schematic Simulation

Minimum Required Versions: Gateway 2.12.10.R, SILOS 4.10.90.R The sixth digital example is a drink machine. This example contains structural and RTL/behavioral forms of Verilog. In this example, specify blocks are

1 week ago

001_and : AND Operation Between Two Layers

Minimum Required Version : Expert 4.14.0.R, Guardian 4.14.0.R This example will demonstrate how a Boolean AND function can be used in Guardian DRC to detect Design Rule Check (DRC) errors