opt_ex12 : HiSIM_HV2 LDMOS Model Extraction

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opt_ex12 : HiSIM_HV2 LDMOS Model Extraction

Requires: Utmost IV, SmartSpice, SmartView

Minimum Versions: Utmost IV 1.10.6.R, SmartSpice 4.17.1.C, SmartView 2.28.2.R

This example describes how to extract a standard HiSIM_HV2 model parameters.
To extract a model which is scalable with geometry, multiple different device sizes must be
included. In this example, three devices with the different channel width are used. And the
device channel length is the drawn poly gate length which overlaps the intrinsic channel
and the drift resistance regions.
The following process parameters are defined in the model library. The values of ldrift1,
ldrif2 and tox are fixed during the optimization.

tox:Physical oxide thickness
nsubc:Substrate impurity concentration
nover:Impurity concentration of loverld at drain, and at source if cosym=1 and
the value is declared
loverld:Overlap length at drain side, and at source if cosym=1
lovers:Overlap length at source side
ldrift1:Length of light doped drift region at drain, and at source if cosym=1
ldrift2:Length of heavily doped drift region at drain side, and at source if cosym=1
xldld:Gate-overlap length at drain side

The project file
opt_ex12.prj
and the data file
opt_ex12.uds
for this example should be loaded into your database. When opened, the project will look
as shown in
opt_ex12_project.png
.

The optimization sequence, which fully automates the extraction of HiSIM_HV2 model parameters,
consists of nine sections. The section one and two extract the threshold voltage region model
parameters of HiSIM_HV2. The third section is prepared to get the initial model parameters
for the substrate current model. The section four aims to optimize the drift region resistance
parameters and the low field mobility parameters at the small drain and the gate voltages.
The bias dependency of the drift region resistance is optimized in the section five to fit the drain
current versus the drain voltage characteristics. This completes the reference geometry model
parameter extraction at the room temperature.
The section six through the eight optimize the geometry and the temperature scaling model parameters
to complete the scalable HiSIM_HV2 model over the temperature change. The section nine is to get
the gate capacitance characteristics.
The green and red curves of the plots show the target data and the simulations, respectively.

Section 1 : idvglin_cap_rtp

This section optimizes the parameters of the threshold voltage region for the ldmos reference
geometry device. The data in this section is the drain current versus the gate voltage
characteristics in the linear region and the cgg and cgs capacitance characteristics at the room
temperature.
The following model parameters are extracted.

nsubc:Substrate impurity concentration
vfbc:Flat band voltage
muecb0:Coulomb scattering
muecb1:Coulomb scattering
mueph0:Phonon scattering
mueph1:Phonon scattering
xldld:Gate-overlap length at drain side
loverld:Overlap length at drain side, and at source if COSYM=1
lovers:Overlap length at source side
nover:Impurity concentration of LOVERLD at drain, and at source if COSYM=1
vfbover:Flat-band voltage in overlap region
cgso:Gate-to-source overlap capacitance
cgdo:Gate-to-drain overlap capacitance

After this step has been completed, the fit to measured data will be as shown in
opt_ex12_01.png
.

Section 2 : idvglin_warray_rtp

In this section, the parameters for narrow width effect are optimized using
the devices of multiple width values. The following model parameters are extracted.

nsubcw:Modification of substrate concentration for narrow width
wl2:Threshold voltage shift due to small size effect
wvth0:Threshold voltage shift
muephw:Width dependence of phonon mobility reduction

Also, the following model parameters used at the previous step are included in this
section to ensure the entire fitting.

muecb0
muecb1
mueph0
mueph1

After this step has been completed, the fit to measured data will be as shown in
opt_ex12_02.png
.

Section 3 : idvglin_idvd_ref_rtp

The section aims for getting the initial values of the substrate current model and
the channel length modulation parameters using the drain current versus the drain voltage
at the lowest vgs voltage.
The following model parameters are extracted.

ndep:Depletion charge contribution on effective-electric field
ninv:Inversion charge contribution on effecitve-electric field
bb:High-field-mobility degradation
sub1:Substrate current coefficient of magnitude
sub2:Substrate current coefficient of exponential term
svds:Substrate current coefficient of exponential term
svgs:Substrate current dependence on vgs
clm1:Hardness coefficient of channel/contact junction
clm2:Coefficient of qb contribution
clm3:Coefficient of qi contribution
sc2:Vds dependence of short-channel effect