opt_ex11 : HiSIM_HV LDMOS Model Extraction

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opt_ex11 : HiSIM_HV LDMOS Model Extraction

Requires: Utmost IV, SmartSpice, SmartView
Minimum Versions: Utmost IV 1.10.6.R, SmartSpice 4.10.2.R, SmartView 2.28.2.R
This example describes how to extract a standard HiSIM_HV model (level = 73) parameters.
To extract a model which is scalable with geometry, multiple different device sizes
must be included. In this example, three geometry devices are included.
The project file
opt_ex11.prj
and the data file
opt_ex11.uds
for this example should be loaded into your database. When opened, the
project will look as shown in
opt_ex11_project.png
.
The optimization sequence, which fully automates the extraction of HiSIM_HV
model parameters, has eight sections. The section one and two extract the threshold
region model parameters of HiSIM_HV. The third section is prepared to get the
initial model parameters for the substrate current model of HiSIM_HV. The section
four aims to optimize the drift region resistance parameters at the small drain
voltage. The bias dependency of the drift region resistance is optimized in the section
five. This completes the reference geometry model parameters at the room temperature.
The section six to eight optimize the geometry and the temperature scaling model
parameters to complete the scalable HiSIM_HV model over the temperature change.
Section 1 : idvglin_cap_rtp
This section optimizes the parameters for the ldmos reference geometry device. The
data in this section is the drain current versus gate voltage characteristics
in the linear region and the cgg capacitance characteristics at the room temperature.
The following model parameters are extracted.
nsubc Substrate impurity concentration
vfbc Flat band voltage
ninv Inversion charge contribution on effective-electric field
ndep Depletion charge contribution on effective-electric field
muecb0 Coulomb scattering
muecb1 Coulomb scattering
mueph0 Phonon scattering
mueph1 Phonon scattering
loverld Overlap length at drain side, and at source if cosym=1
lovers Overlap length at source side
nover Impurity concentration of loverld at drain, and at source if cosym=1
vfbover Flat-band voltage in overlap region
After this step has been completed, the fit to measured data will be as shown in
opt_ex11_01.png
.
Section 2: idvglin_warray_rtp
In this section, the parameters for narrow width effect are optimized using
the devices of multiple width values. The following model parameters are extracted.
nsubcw Modification of substrate concentration for narrow width
wl2 Threshold voltage shift due to small size effect
wvth0 Threshold voltage shift
muephw Width dependence of phonon mobility reduction
Also, the following model parameters used at the previous step are included in this
section to ensure the entire fitting.
nsubc
vfbc
mueph0
mueph1
After this step has been completed, the fit to measured data will be as shown in
opt_ex11_02.png
.
Section 3 : idvd_warray_rtp
The section aims for getting the initial values of the substrate current model parameters.
The following model parameters are extracted.
sub1 Substrate current coefficient of magnitude
sub2 Substrate current coefficient of exponential term
svds Substrate current coefficient of exponential term
svgs Substrate current dependence on Vgs
clm1 Hardness coefficient of channel/contact junction
clm2 Coefficient for QB contribution
clm3 Coefficient for QI contribution
clm5 Effect of pocket implantation
clm6 Effect of pocket implantation