Simulation Standard

1. Introduction The topography simulation module, Elite has constantly been improved in order to simulate advanced processes, which are becoming more complex with device miniaturization and further integration of VLSI

Polysilicon thin film transistors are attractive as active devices in driver circuits of highly integrated active-matrix liquid crystal displays (AMLCDs) and as p-channel metal-oxide-semiconductor field effect transistors (MOSFETs) in static

The Input/Output Buffer Information Specification (IBIS) is a standard for electronic behavioral models based on I/V and V/T curve data. It is being developed by the IBIS Open Forum, which

A powerful new feature “Stop-Continue” has been added to SmartSpice to allow the user to suspend a transient simulation and investigate the output before resuming the simulation run from the

Silvaco has always supported the Solaris based Cadence design environment for seemless SmartSpice integration. To accommodate new customer demands to support the new Linux environment, Silvaco has developed a SmartSpice

A new notation has been introduced into SmartSpice to allow a compact expression of a multiple bit wire buss to be used. From this expression the user can simply state

Netlist extraction and the quality of netlist extraction is becoming of increasing concern for integrated circuit design flow. As circuits become more complicated with concomitant reductions in geometry, the design

HIPEX-R is part of HIPEX software package for physical verification of multimillion transistor designs. It is a hierarchical full chip parasitic resistance extraction tool.

SILVACO is releasing its new layout parameter extractor: HIPEX-NET. The new tool will replace Silvaco’s Maverick, which is a part of Guardian LVS/ERC. While being fully compliant with Maverick, HIPEX-NET

In previous versions of Guardian DRC there were only two ways of measuring the distance between two segments: the ordinary, Euclidean metric, and the square metric, which behaves differently when