Library Webinars

As semiconductor technology advances, the impact of on-chip variation increases, which means more sophisticated solutions are required.

Designers today see a significant increase in the number of simulations and PVT corners required to an accurate library characterization, including new formats to support process variations, that can be

This webinar will present an efficient methodology for migrating and optimizing standard cell libraries. Foundation IP reuse through migration between non-disruptive technology nodes can save a lot of engineering resources