On-Chip Variation and the Sign-off Timing Flow: An Industry Perspective
As semiconductor technology advances, the impact of on-chip variation increases, which means more sophisticated solutions are required. Those solutions need to take into account a variety of issues, including feasible run times in production usage and how to reduce pessimism. Each new approach by the industry is intended to reduce over-pessimism from the previous approach, but all come with trade-offs. In this talk, we present the industry perspective on these major challenges. We cover the progress leading up to the current accepted solutions, as well as what comes next. We also discuss how Silvaco is addressing these leading-edge challenges.
What attendees will learn:
- What variation means in the context of library characterization
- What on-chip variation is and its different causes
- Inter-chip variation
- Intra-chip variation
- Review of different industry approaches to account for on-chip variation
- OCV, AOCV, LVF
- Their advantages and limitations
- Current industry standards for variation-aware libraries
- The improvements needed to handle leading-edge technology nodes
- The characterization challenges involved in creating variation-aware libraries
- Silvaco solutions for variation-aware library characterization
Bernardo Culau is Director of Library Characterization at Silvaco. He joined Silvaco in 2018 as part of the acquisition of Nangate, where he had worked for nine years. At Nangate he developed EDA tools for library characterization and delivered standard cell library IP for multiple foundries and technology nodes. Bernardo holds Computer Engineering degrees from Universidade Federal do Rio Grande do Sul, Brazil and from Grenoble INP, France.
When: October 10, 2019
WHO SHOULD ATTEND:
Academics and engineers interested in learning more about on-chip variation effects and the methodologies used by the industry to handle them. Engineers and managers seeking efficient ways to have accurate variation-aware libraries.