Latest Software Baseline Release Notes
The release notes linked below contain the latest changes and new features of every version of our products in the latest software baseline.
Analog/Mixed-Signal Simulation and SPICE Device Modeling |
Product | Description | Version |
---|
SmartSpice | Parallel SPICE simulator | 5.0.3.R |
SmartSpice Pro | Fast Circuit Simulator | 5.0.3.R |
SmartSpice RF | Frequency and Time Domain RF Circuit Simulator | 5.0.3.R |
SmartView | Waveform viewer and simulation analysis | 2.2106.1.R |
Utmost IV | Device characterization and SPICE modeling | 2.14.0.R |
TechModeler | Device modeling for new technologies using only device behavior | 2018.1.0.R |
Spayn | Statistical parameter and yield analysis tool for models and tests | 2.14.0.R |
VarMan | Variation-aware design solution | 2021.2.1.R |
Custom IC CAD |
Product | Description | Version |
---|
Gateway | Hierarchical schematic editor | 4.2106.0.R |
Expert | Hierarchical IC layout editor | 5.2106.0.R |
Guardian LVS | Physical verification of LVS | 4.10.17.R |
Guardian DRC | Physical verification of DRC | 5.2106.0.R |
Guardian Net | Physical verification of layout networks with LVS | 5.2106.0.R |
SmartDRC/LVS | Physical verification DRC/LVS | 1.2107.R |
Hipex | Full-chip parasitic extraction | 3.8.3.R |
SiCure | IR, EM and Thermal Analysis | 1.07.14.R |
Digital CAD |
Product | Description | Version |
---|
Silos | Verilog simulator | 4.16.17.R |
HyperFault | Verilog IEEE-1364-2001 compliant fault simulator | 4.16.17.R |
AccuCell | Cell characterization and modeling | 3.0.12.R |
AccuCore | Block characterization, modeling and STA | 3.0.7.R |
Spider | Netlist-to-GDSII place-and-route design flow | 1.8.3.R |
Parasitic Extraction |
Product | Description | Version |
---|
Clever | RC extractor for realistic 3D structures | 3.11.26.R |
Extracted Netlist Analysis and Reduction |
Product | Description | Version |
---|
Jivaro | RCLK parasitic reduction for post-layout netlist | 2021.1.21.R |
Viso | Parasitic analyzer | 2021.1.125.R |
Belledonne | Layout comparator | 2021.1.125.R |
Brenner | Layout comparator and debugger | 2021.1.125.R |
TCAD |
Product | Description | Version |
---|
Victory Atomistic | Atomistic simulator | 1.4.0.R |
Victory Process | 3D process and stress simulator | 7.58.3.R |
Victory Device | 3D device simulator | 1.18.0.R |
Victory Mesh | Mesh integration between process and device or interconnect tools | 1.8.2.R |
Athena | 1D and 2D process and stress simulator | 5.22.3.R |
Atlas | Device simulation of material-based devices | 5.32.1.R |
Virtual Wafer Fab | Perform Design of Experiments (DOE) and optimization experiments | 2.12.24.R |
DeckBuild | Create, edit and run TCAD simulation input files | 5.2.14.R |
DevEdit | Ceates and edit mesh structures for 2D or 3D simulators | 2.8.26.R |
MaskViews | Layout editor for GDS2 or Silvaco’s layout format | 3.2.27.R |
TonyPlot | Visualization tool for 1D and 2D TCAD structures | 3.10.26.R |
TonyPlot 3D | Visualization tool for 3D data from TCAD and parasitic extraction | 3.10.68.R |
Victory Visual | Visualization tool for 1D, 2D and 3D TCAD structures | 1.0.8.R |
Foundation IP |
Product | Description | Version |
---|
Viola | NG tool suite Viola 221_12-QR03 | 2021_12-QR03 |