Low Power Foundation IP Solution
Silvaco offers a complete portfolio of Low Power Foundation IP for silicon foundries and designers of ASICs and SoCs:
- Memory Compilers for SRAMs, ROMs, and Register Files
- Standard Cell Libraries for digital logic
For over 25 years Silvaco has been providing Foundation IP to the design community. Silvaco is committed to offering best-in-class Low Power Foundation IP and associated services and is a one-stop shop for chip developers, fabless companies, and foundries.
Standard Cell Libraries
The Silvaco 7T (seven track) standard cell library provides a highly optimized IP for the GlobalFoundries 55nm LPx process node, targeting low power and high-density applications.
The Silvaco 7T Library offers thousands of cells consisting of approximately 650 regular standard cells, more than 150 additional cells for low power and high speed and multiple gate length variants. Most are available in five VTs. They also come in twin/triple well options. This enables designs for applications from ultra-low power to high-speed.
The Silvaco 7T library is extended with a Power Management Kit, taking power reduction to the next level with features such as multi-voltage design and power gating.
The Silvaco GF 55LPx Standard Cell Library provides the ability to combine multiple low power strategies to obtain compounded power savings.
- Power gating provides coarse grain block shutdown
- Level-shifters enable multiple voltage domains, giving the flexibility of 1.2V and 0.9V operation for optimal performance at low power
- Low leakage cells with long gate channel offer a low static power vs performance trade-off.
- Fine grain drive strengths provide more cell options during synthesis, reducing the usage of oversized cells
Standard Cells Features and Benefits
|Multiple Vt and Well options||Customize designs for optimal low power performance and area implementation|
|Fine grained drive strengths and low leakage cells||Better low power implementation of designs|
|Power Management Kit||Enables power gating and multi voltage low power design methodologies|
|Multi-bit and Multi-height standard cells||Better design implementation with sequential cells and MUX structures|
|ECO kit with fixed pattern for FEOL layers||Enables the flexibility of late layout modifications with minimal number of mask changes|
|STRATEGY||DYNAMIC POWER SAVINGS||STATIC POWER SAVINGS|
|Multiple Voltage Domains||High||High|
|Low Leakage Cells||–||Medium|
|Fine Grain Drive Strengths||Medium||Low|
Silvaco’s best in class Single Port SRAM in the GF 55LPx process is designed to achieve minimum area and power while meeting aggressive timing requirements.
The silicon proven memory which uses High Density Pushed Rules foundry bitcell has industry leading low Dynamic Power consumption, and multiple modes for extensive Static Power saving with low leakage.
Other features include Embedded Retention Switch option which provide flexibility and low power operation. It includes Transition Ramp Controller (TRC) that enables control and drastic reduction of the inrush current. Variable write mask and other standard optional features are also available.
Memory Power Management
Multiple power modes for static power savings are available providing the flexibility to select the best trade-off between power saving and wake up time. Retention, retention-nap, and shut-down modes provide a progressive reduction of leakage power compared to stand-by mode.
Silvaco design architecture enables low power consumption through multiple compiler options.
Memory Features and Benefits
|Multiple Vt periphery||Architecture customized to provide better optimized target power, performance, area envelop|
|Embedded power switches||Saves SoC design time, area, and power while lowering risk|
|Segmented power control||Provides flexibility for segment power shut off and overall power management|
|Read and Write Assist||Low voltage and low power operation|
|Multiple power management modes||Offers multiple power saving customization options|
|Single power supply option||Easy integration|
Silvaco Memory and Standard Cells in GF 55 LPx are in volume production at multiple customers. Silicon report is available for Standard Cells.
Silvaco offers a 30-day evaluation where customers can get access to Front End + LEF kit for PPA analysis.
For more information on Silvaco embedded memory, standard cell library, or I/O Foundation IP, contact Sales@silvaco.com or Contact a Silvaco representative for information.