The SmartSpice Interface to Cadence (revisited)
The SmartSpice interface to the Cadence Design Framework II has been substantially improved in its latest release (version 1.0.8.R), following feedback from a number of existing users. The interface is implemented through the Cadence Spice Socket, and enables users of Cadence’s Analog Artist and Composer software to interact directly, and seamlessly, with SmartSpice. The interface works through a series of Analog Artist control screens implemented by Silvaco using the Cadence OASIS interface. Because it depends on the sophisticated functionality provided by OASIS, the SmartSpice/Spice Socket interface is only compatible with version 4.4.0 (and above) of the Design Framework. SmartSpice is also compatible with the HSPICE Socket built into older versions of Cadence’s Composer, Edge and Artist products, although access through this interface to SmartSpice’s more powerful features is necessarily limited. The improvements described in this article take the form of a series of enhancements (including some bug fixes) which have been made to several of the existing interface features. These improvements are part of an on-going project aimed at making the SmartSpice interface provide access to substantially more of the features available in SmartSpice itself than was the case in earlier releases.
One important feature, fixed in this release, is the generation of hierarchical netlists from Analog Artist, and the ability to correctly annotate sub-circuit simulation information back to the Composer schematic window. The ability to annotate operating points and currents has also been fully implemented for all component types. An example of a fully annotated subcircuit is illustrated in Figure 1. The functionality of the analysis control screens in Analog Artist will be greatly enhanced in the next release of the SmartSpice interface; the first step in this direction has already been taken in the current release, however, in the form of a set of control items providing the ability to save bias points in both DC and transient analyses.