• Webinars

Accelerating Manufacturing-Aware Simulations for Photonic Integrated Circuits with FTCO™ and Digital Twins

Manufacturing-aware PIC simulation workflow using FTCO digital twin modelingPhotonic integrated circuit (PIC) designers face a persistent challenge: devices that perform well in simulation often underperform after fabrication. Manufacturing introduces geometric variations—line-edge roughness, angled sidewalls, critical dimension shifts, corner rounding, and non-uniform core thicknesses—that significantly impact effective index, mode confinement, insertion loss, and coupling efficiency. Traditional FDTD simulations on idealized, as-drawn geometries tend to overestimate device performance, while their computational cost limits thorough sensitivity analysis.

This webinar presents Silvaco’s manufacturing-aware photonic simulation workflow, which closes the gap between design intent and fabrication reality. By importing fab-specific process parameters, designers can accelerate simulating devices as manufactured and evaluate real-world performance before tapeout. The integrated FTCO solution—Victory Process for physics-based 3D modeling of fabrication steps, Victory Device for GPU-accelerated FDTD simulation, Victory DoE for efficient parameter space exploration, and Victory Analytics for AI-powered analysis, optimization, and surrogate modeling—provides a seamless flow from GDS import to digital twin creation. Practical case studies on passive devices demonstrate how this approach helps designers to accelerate the identification and mitigation of  fabrication-induced performance degradation early in the design cycle.

What You Will Learn

  • How manufacturing variations impact photonic device performance and why idealized simulations can be misleading
  • How to simulate photonic devices as manufactured using fab-aware process parameters
  • How to build a complete workflow from GDS import to digital twins using Silvaco’s integrated AI-powered FTCO solution to accelerate PIC development
  • How to perform sensitivity analysis and optimization to mitigate fabrication-induced performance degradation

Presenter

John Sembower
Field Application Engineer, Silvaco

John is a Field Application Engineer at Silvaco specializing in photonics simulation, FDTD workflows, and integrated photonic device modeling. He works with customers on electromagnetic simulation, GPU-accelerated photonics analysis, inverse design, design-of-experiments studies, and process-aware device validation. His technical interests include silicon photonics, adjoint optimization, waveguide device design, and scalable simulation workflows. John holds degrees in Physics and Astronomy from the University of Colorado Boulder, with minors in Quantum Engineering and Applied Mathematics

WHO SHOULD ATTEND:

PIC designers, device simulation engineers, product managers, and engineering management.

When: July 9, 2026
Where: Online
Time: 10:00 Santa Clara
Time: 11:00 Paris
Time: 10:00 Beijing
Language: English

Register!

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