Broad IP Portfolio - IP Management

Proven Secure Automotive, Interface and Processors IPs

High-speed PHYs and I/Os for FinFET and FDSOI Nodes​

AMBA Secure Subsystems for IoT​

Advanced Memory Interfaces – HBM2e, Combo DDR, 56G SerDes

Optimized Foundation IP for 180 to Sub-12 nm Nodes

Enterprise-level IP Management Solution​

Broad IP Portfolio - IP Management

Proven Secure Automotive, Interface and Processors IPs

High-speed PHYs and I/Os for FinFET and FDSOI Nodes​

AMBA Secure Subsystems for IoT​

Advanced Memory Interfaces – HBM2e, Combo DDR, 56G SerDes

Optimized Foundation IP for 180 to Sub-12 nm Nodes

Enterprise-level IP Management Solution​

실바코의 IP 제품 및 솔루션은 임베디드 프로세서, 유선 인터페이스, 버스 패브릭, 주변기기 컨트롤러와 자동차, 소비자 가전 및 IoT/센서 애플리케이션용 코어를 포함합니다. 삼성 파운드리의 디자인 IP는 이제 실바코가 라이센싱 및 지원을 제공합니다. 본 IP 카탈로그는 유선 고속 인터페이스, 아날로그, 믹스드 시그널 블록을 비롯하여, 다양한 소비자 가전, 모바일 및 HPC 애플리케이션의 요구를 충족합니다.

1

Interface PHYs

2

Interface Controllers

3

Automotive Controllers

4

AMBA IP Cores and Subsystems

5

Security Cores

6

Analog Cores

7

Embedded Processors

8

Foundation IP

9

Xena IP Management

특정 IP에 대한 추가 정보가 필요하거나 필요한 IP 찾을 수 없으면 실바코에 문의하여 주십시오. 

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동영상

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Everything You Want to Know about Silvaco Foundation IP

고객의 평가

Rick Lazansky
 Over the past two years, Silicon Catalyst has been working with key industry players to develop a complete ecosystem that economically and effectively supports the new wave of semiconductor startups that we are seeing today. Our Portfolio Companies have consistently been requesting IP as the critical element that we had not been able to deliver. Silvaco’s offering fulfills a real hole that has been impeding the success of these startups. We are glad to deliver this capability as we continue to build the semiconductor start up ecosystem. 
Srinath Anantharaman
 The integrated solution enables design teams to collaborate efficiently in a secure design environment when developing their IPs or SoCs either locally or across multiple design sites. It enables design teams to successfully tapeout their designs by mitigating the risk by sharing and using the correct version of the design data and IPs.