Fast and Integrated Quantum Transport Solution for GAA-NS-FET Design Exploration & Optimization at Full-Device Scale

Abstract

As CMOS technology scales toward the 2nm node and beyond into the Ångström era, Gate-All-Around Nanosheet FETs (GAA-NS-FETs) have become the architecture of choice for next-generation logic devices. At these dimensions, quantum effects can no longer be neglected, and the electronic band structure becomes device-dependent. In this webinar, we show how Silvaco’s Victory Atomistic – a quantum transport device  simulator – can be used to fulfil these requirements. Victory Atomistic is built on the Non-Equilibrium Green’s Function (NEGF) formalism with a full tight-binding band structure. Thanks to a proprietary Low Rank Approximation (LRA) technique and an optimized semi-unitary matrix database, Victory Atomistic achieves up to 10⁵–10⁶× speed-up over conventional NEGF solvers, allowing the simulation of a full nanoelectronic device whilst delivering full-band accuracy at effective-mass speed. We demonstrate how Victory Atomistic, seamlessly integrated with Silvaco’s leading AI-powered FTCO™ workflow based on Victory DoE and Victory Analytics, forms a fast and integrated quantum transport solution which enables rapid prototyping as well as design exploration and optimization of GAA-NS-FETs — including key figures of merit such as DIBL, V_th, SS, and injection velocity — across a wide range of geometries, materials, and temperatures.

What You Will Learn

• Why quantum transport simulation using NEGF is essential
• How Victory Atomistic achieves fast simulation turnaround times and high fidelity
• How to set up and run a GAA-NS-FET simulation end-to-end
• How Victory Atomistic can be used in familiar device optimization and FTCO workflows

Presenter

Dr. Philippe Blaise
Principle Engineer, Silvaco

Dr. Philippe Blaise is a Principle Engineer in Silvaco’s TCAD Business Unit and leads the Victory Atomistic developments. Prior to joining Silvaco, Dr. Blaise was a Senior Engineer specialized in atomistic simulation of emerging memory devices and transistors at CEA/LETI for 15 years. He is a former member of the IEEE IEDM Modelling and Simulation Committee. He published more than 60 journal articles and 30 conference contributions as well as 5 patents. Dr. Blaise holds a master’s degree in applied mathematics from ENSIMAG, France and a Ph.D. in solid states physics from the Université Grenoble Alpes, France.

WHO SHOULD ATTEND:

Device simulation engineers, product managers, and engineering management.