Simulation Standard

Know how your circuit behaves across process variation before silicon tells you, with Monte Carlo-accurate results up to 30X faster.

24 years ago

A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits

This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is also formulated and shown

24 years ago

Behavioral Modeling and Simulation in the Scholar Schematic Environment

This article focusses on the use of Silvaco International’s schematic capture and editing tool Scholar combined with Verilog A. Verilog A is a standard language used for behavioral level modeling.

24 years ago

SmartView – Integration Aspects and Key Attributes

This simulation standard will discuss Silvaco International’s post processing application SmartView and will highlight features that identifying it as an important tool to the design engineer. In particular, the integration

24 years ago

Getting an Accurate FFT Spectral Plot in SmartSpice

The transient simulation uses an adaptive time-stepping algorithm depending on the change in the circuit waveforms (dV/dT). This means the simulated waveform consists of uneven time steps (more time points

24 years ago

Real-time DRC Verification by DRC Guard

DRC Guard Performs "real-time" DRC on Expert Layout Editor. DRC Guard’s real-time design rule check (DRC) verifies entered or modified objects after the objects are edited. DRC Guard detects and

24 years ago

Actual Examples of Creating Parameterized Cells

Silvaco’s Expert tool is an extremely powerful layout-editing tool that supports features related to parameterized cells. Parameterized cells, often called P-cells, increase designer productivity by adding enormous flexibility and efficiency

24 years ago

Connectivity Operations in Guardian DRC

The article "Connectivity options for DRC spacing check operations in Guardian" (Simulation Standard, vol. 11, no. 12) [1] describes layout netlist connectivity based on DRC checks. Earlier versions of Silvaco

24 years ago

How does Snap-to-grid Works for Cell Instances

We have lots of cells that become off-grid when we do cut-and-paste from other cells. We tried to use the "Tools->Snap Selected to Grid" command, but the cell doesn't get

24 years ago

Simulation of Single-Event Effects in FinFETs Using the ATLAS Device Simulator

A great deal of recent industry attention has focused on the use of non-planar multi-gate device structures in future generation MOS devices that feature channel lengths below about 50 nm

24 years ago

Simulation of a Double Ridge Edge Emitting InGaAsP/InP MQW Laser

In order to investigate the influence of ridge separation on the transverse optical modes of a double ridge edge multiple quantum well (MQW) emitting laser, we have designed a generic