Simulation Standard

This article presents an overview of new features added to Silvaco's Expert layout editor. Silvaco has taken a careful look at the real-world obstacles faced daily by semiconductor layout designers

Recent versions of Guardian DRC introduce operations that involve edge layers, either on input or on output. An edge layer is a layer that contains line segments that are edges

We introduce a platform-independent version of Guardian LVS. An important feature of any tool is its capability to operate on various platforms and to support internationalization. Now Guardian LVS is

Q: I have some trouble counting the number of in-stances in a layout using Expert. I have tried to use the Chip Rover feature

Silvaco’s Binary Collision Approximation (BCA) Monte- Carlo Implantation simulator closely replicates the physics of implantation by individually tracking implanted ions and their resulting interstitial and vacancy damage as the ions

This article will present two different ways to extract parasitics from an IC design: first using a full chip extraction tool HIPEX-RC based on geometrical information, then using a field

Q: Can ATLAS simulate an SEU event in 2D? To simulate a single event upset (SEU) is inherently a 3D problem because the alpha particle may strike the chip at

RPI VCSEL model was developed by Professor Michael Shur and his team from the Rensselaer Polytechnic Institute (RPI) [1]. A release of this model has been implemented within SmartSpice, and

Berkeley University BSIM3v3 model is the industry-standard, physics-based, deep-submicron MOSFET model for digital and analog circuit designs. This makes BSIM3v3 model a good candidate for implementation in Verilog-A HDL for