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2019

Know how your circuit behaves across process variation before silicon tells you, with Monte Carlo-accurate results up to 30X faster.

7 years ago

SmartSpice Does It Smart

By this definition, any SPICE simulator qualifies as a smart design tool, but what about versatility? SmartSpice has had over 30 years of product development and is the Swiss Army

7 years ago

AIおよびマシン・ラーニングのSoC – メモリおよびインターコネクトIPの視点

本ウェビナーでは、人工知能 (AI) およびマシン・ラーニング (ML) のSoCを開発する上での課題について考察します。

オンチップばらつきおよびサインオフ・タイミング・フロー: 業界の視点

本ウェビナーでは、これらの主要な課題に関する業界の視点についてお話しします。現在認められているソリューションにつながる進歩について、そして次に来るものについて説明します。

7 years ago

Maverick: Hierarchical Netlist Extractor for PC Platforms

Diamond is considered to be the ultimate semiconductor material for high power and high frequency devices due to its superior electrical and thermal properties, such as high breakdown field, high

7 years ago

MEDIA ALERT: Meet Silvaco at the TSMC OIP Ecosystem Forum

September 18, 2019

7 years ago

シルバコ、HDL Design HouseとアナログおよびデジタルICデザイン・サービスで提携

米国カリフォルニア州サンタクララ発 – 2019年9月16日 - HDL Design HouseとSilvaco, Inc. (以下、シルバコ) は、本日、アナログ/デジタルICデザイン・サービス、そしてフルターンキー・ソリューションを世界中の半導体ファブレス企業に提供するべく協業することを発表しました。

7 years ago

The Need for Advanced Wide Bandgap Power Electronics

PowerAmerica’s strategic roadmap for next generation wide bandgap (WBG) power electronics (PE) came out earlier this year. The public version of the roadmap includes a background/introduction and market forecast pertaining

7 years ago

Next Generation CMOS Nanowire: From Atoms to Circuit Simulation

Abstract— A complete simulation flow for a Nanowire-based ring oscillator circuit is presented, where the active devices were simulated using an atomistic device simulator. The results of this simulation have

7 years ago

3D TCAD Simulation for Power Devices

y first IC design back in 1978 was a DRAM and it ran on 12V, 5V and -5V, but then my second DRAM was using only a 5V supply. Today

7 years ago

Optimization of Select Gate Transistor in Advanced 3D NAND Memory Cell

Abstract—There are several device challenges unique to the select gate transistor in 3D NAND memory cell. It requires low leakage current to prevent read and program disturb problems and it