2022/2/11 | 3:00 am – 3:30 am (JST)
本ウェビナーでは、FinFET スタンダード・セルのレイアウト設計における課題をいくつか取り上げ、シルバコの Celloを使用して、これらの問題に対処する方法を説明します。
/wp-content/uploads/2019/11/silvaco-logo.png00Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2022-01-21 13:27:142022-03-07 20:39:30Managing the Complexity of FinFET Standard Cell Layout with Cello
2021/9/10 2:00 am – 2:30 am (JSD)本ウェビナーでは、モバイルやIoTアプリケーションをターゲットとする「SPI」(Serial Peripheral Interface)信号を使用するメモリ・デバイスに焦点を当てます。
/wp-content/uploads/2019/11/silvaco-logo.png00Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2021-08-17 09:06:282021-09-13 18:10:11Designing with Silvaco’s Octal SPI Memory Controller with Advanced Memory Support for IoT Systems
本ウェビナーでは、シルバコのLow Power Foundation IPの概要と、低消費電力設計に役立つ手法やテクニックをご紹介します。
/wp-content/uploads/2019/11/silvaco-logo.png00Gigi Boss/wp-content/uploads/2019/11/silvaco-logo.pngGigi Boss2021-06-03 14:18:592021-08-04 21:59:44Achieving Extreme Low Power IoT Designs with Silvaco’s 55LPx Foundation IP Solution
/wp-content/uploads/2019/11/silvaco-logo.png00Erick Castellon/wp-content/uploads/2019/11/silvaco-logo.pngErick Castellon2021-01-17 22:49:162021-08-04 22:04:00How to Design Ultra-low Power Embedded Memories with Silvaco Memory Compilers
January 14, 2021 | 10:00 am – 10:20 am (PST)
In this webinar, Sharmistha Sinha and Anand Mishra share their analysis and experience with Cello done at ST on multiple technologies.
/wp-content/uploads/2019/11/silvaco-logo.png00Erick Castellon/wp-content/uploads/2019/11/silvaco-logo.pngErick Castellon2020-12-14 16:06:532021-08-04 22:01:33Reducing the Layout Development Cycle Time for Standard Cells
/wp-content/uploads/2019/11/silvaco-logo.png00Erick Castellon/wp-content/uploads/2019/11/silvaco-logo.pngErick Castellon2020-07-09 18:13:212021-08-04 22:03:01How to Secure an AMBA AHB Subsystem for the ARM Cortex M3 Processor
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