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2017

Know how your circuit behaves across process variation before silicon tells you, with Monte Carlo-accurate results up to 30X faster.

9 years ago

TCAD Simulations of TFET and Tunneling Diode

Researchers and designers are looking into a future of ultra-low power and ultra-low voltage (ULV) devices and designs. Portable devices, nodes, and sensors, energy harvesting are all examples of devices

9 years ago

TFT Panel Simulation Using SmartSpice Pro

TFT panels have already gained their undisputable reputation in a variety of professional and commercial applications. High quality, ease of customization, and comparably low manufacturing costs position these panels as

9 years ago

TFT、FPDの設計を加速

本ウェビナーでは、これらのシミュレータが大規模な回路ドメインにおいて有効となる主な特徴をいくつか紹介し、イベント・ドリブンかつマルチレート・シミュレータであるシルバコのSmartSpiceProを用いたTFTベースのディスプレイ・パネルのシミュレーション方法について説明します。

9 years ago

TFT、LCD、OLEDディスプレイ設計のためのTCAD活用手法

本ウェビナーでは、TFT、LCD、OLEDディスプレイの設計者にとって有益となる様々なTCADベースのシミュレーション技術を紹介します。

9 years ago

信頼性解析は設計サイクルの初期に先手を打つ

このウェビナーでは、さまざまなタイプのIC開発において設計サイクルの初期段階に、シンプルで必要最小限の入力データを用いて、パワーおよびEM/IRドロップ解析を実行することにより、ロバスト性と使いやすさを保証するベスト・プラクティスを紹介します。

10 years ago

Model Extraction for Body-Biased XDMOS Devices

Compared with regular MOSFET devices, the body bias effect in HVMOS is usually more pronounced. In addition to the regular threshold voltage increase with body bias, the LDD region of

10 years ago

Edge Effect Analysis on TFT Devices Using 3D Numerical Simulation

3D TFT analysis has been getting lots of attention due to issues caused by 3D effects such as the edge effect on the TFT characteristics. The presence of an enhanced

10 years ago

3D Simulation of Dual-Gate Thin Film Transistors

Dual-Gate Thin Film Transistors (DGTFTs) are often used in pixel driver and peripheral circuits for liquid crystal displays. This is because of the reduction of the gate-off state leakage current

10 years ago

Effect of Fin Thickness on Subthreshold Characteristics of 10 nm FinFETs Using 3D TCAD

The planar bulk Si metal-oxide semiconductor field-effect transistor (MOSFET) has reached its scaling limit due to various short channel effects (SCE). With 20 nm advanced planar technology, the source and

10 years ago

寄生素子抽出解析の秘訣が明らかに!

本ウェビナーでは、同一のデザインにおける2つの抽出データの特性を質的および量的に比較するフローを確認します。