3D Simulation of Dual-Gate Thin Film Transistors

1. Introduction

Dual-Gate Thin Film Transistors (DGTFTs) are often used in pixel driver and peripheral circuits for liquid crystal displays. This is because of the reduction of the gate-off state leakage current as well as the kink effect [1,2]. Recently it has been also necessary to consider the problems caused by 3D effects such as the IV characteristics hump effect [3] and leakage current at the edge of the active region [4,5]. This requires 3D simulation of DGTFT characteristics in a reasonable time. However, simulation of DGTFTs is generally difficult, particularly in 3D, because of the electrical floating region between the dual TFTs. This region can cause difficult convergence when calculating the gate-off state characteristics including the Gate-Induced Drain Leakage (GIDL) current. In this article, we demonstrate that our 3D TCAD simulation framework, Victory, can simulate a normal DGTFT and an L-shape DGTFT [2] in 3D accurately, robustly and in a reasonable simulation time.

2. Creation of 3D Dual-Gate TFT structures

The TFT structures have a thin semiconductor region with 50-100nm of amorphous silicon or polysilicon and a gate length/width (Lg/Wg) of 5um/10um. This results in a high aspect ratio (~40) and leads to more difficult mesh generation and device simulation convergence. We created two dual-gate TFT structures using an LPTS (Low-temperature processed polycrystalline silicon) process [2, 6] using our 3D process simulator Victory Process: