Casey Molver

The Monte Carlo Binary Collision Algorithm (BCA) implant module in ATHENA was introduced in an earlier article [Simulation Standard Vol 10, #5, May 1999] which discussed the accuracy of the

A. UTMOST III SOI module has three routines for characterization of the parasitic BJTs of SOI devices. These routines are "IC/VCE", "Gummel" and "INT_BJT" All routines require to have 5

The latest VBIC bipolar model v1.2 of Sep 24 1999 has been integrated into SmartSpice and UTMOST III. It can be invoked by specifying the model selector LEVEL=5 and the

A novel extraction method of high frequency small-signal model parameters for MOSFET is proposed. From S-parameter measurement, this technique accurately extracts the MOSFET model parameters including the charge conservation capacitance

Q: I tried to resize shapes using the DRC command and observed thin "cracks" appeared for polygons with holes (see the left shape in Figure 1). At the same time

In our previous publication ("Scholar: An Enhanced Multi-Platform Schematic Capture", Simulation Standard, Vol.10, Number 9, September 1999) we presented the main features of a new-generation schematic capture tool - Silvaco's

A: ATLAS/S-Pisces and ATLAS/Blaze both have a small signal ac analysis capability built into them. This analysis is based upon the work of S.Laux [1] and results in the extraction

Thyristors are semiconductor devices that exhibit multi-stable or bi-stable electrical characteristics, and can be switched between a high-impedance OFF state and a low-impedance ON state. Bidirectional thyristors are particularly useful

Ever decreasing minimum geometries in MOSFET design results in a corresponding reduction in the thickness of the gate oxide. This is an inevitable result of the increasing doping levels in

With the continuing emergence of optical technologies, optoelectronic device structures are becoming increasingly important for modern telecommunications and data network applications. Like other semiconductor technologies, two-dimensional numerical simulation can be

SOI technology for state of the art CMOS technology is rapidly approaching maturity. PD-SOI device design has the advantage of easier manufacturing but requires more sophisticated device and circuit design

A. It is likely that there may be some contact problems or defected devices during the data collection. This problem can occur when the log file is open and some