SRAM Compiler
Single and dual port SRAM compilers
Silvaco’s SRAM compilers give SoC teams single- and dual-port embedded SRAM IP, configured per instance on named TSMC, GlobalFoundries and UMC processes, so the memory fits your chip instead of the other way round.
SRAM compiler capabilities
Pick the variant that suits your power budget, then build the rest
of the memory around it.
Optimization
Choose a low-power, general-purpose or high-performance variant. Multiple power modes let you trade leakage against wake-up time, and several threshold-voltage (Vt) options and operating modes set how fast the array runs.
Architecture
Low-power operation comes first in the design, with a high-density option for when area is the tighter limit. Nap, Retention and Nap plus Retention modes are there at 55 nm, 40 nm and below. Embedded power switches give you finer control, and you can run one supply or a separate rail for periphery and core.
Yield and integrity
The compilers are verified against both global and local variation. Add ECC bits, and use flexible word size and addressing for redundancy. Where you need them, add a configurable write mask and built-in self test and repair (BIST/R).
Process coverage
Twelve compilers carry part numbers in the current catalog, from 22 to 130 nm across TSMC, GlobalFoundries and UMC. The technology behind them spans 180, 152, 130, 110, 90, 85, 65, 55, 40, 28 and 22 nm, on G, LP and SOI CMOS and on high-voltage, BCD and eFlash offerings. If your process isn’t among them, the compilers port.
Power and area
The operating modes cut power consumption by up to 50%. Partitioned arrays stretch battery life, data retention mode lowers leakage current, and the high-density build saves area.
Low-power modes
Idle memory still leaks. These modes let you decide how much,
against how long the next access can wait.
| Mode | Core | Periphery | What happens | Wake-up | Leakage vs Standby |
|---|---|---|---|---|---|
| Active | On at Vdd | On at Vdd | Reads and writes. Dynamic power plus a little leakage. | — | — |
| Standby | On at Vdd | On at Vdd | Powered, not accessed. Leakage only, no dynamic power. | Quick | 1.00× |
| Nap | On at Vdd | Off | Source biasing on. An intermediate low-power state. | One clock cycle, slightly slower than Standby | 0.69× |
| Retention | Below Vdd | Off | Core held at the lowest voltage that keeps its data. | Slow: periphery switches and circuits power up first | 0.54× |
| Retention + Nap | On at Vdd | Off | Source biasing on, core at nominal voltage. | Slow: periphery switches and circuits power up first | 0.28× |
| Shutdown | Off | Off | Everything off. Data is lost. | Slowest | 0.1× |
Leakage is relative to Standby, as Silvaco publishes it for a 4Kx32 instance at the typical corner, 1.2 V and 25 °C. Nap, Retention and Retention +
Nap are available at 55 nm, 40 nm and below. Which modes a given compiler carries is worth confirming with an IP specialist.
Where the SRAM compiler fits
Low-power SoC caches and buffers
Nap and Retention hold data while cutting leakage between accesses.
Battery-powered and IoT designs
Array partitioning and a retention mode keep standby drain low.
High-performance compute blocks
High-performance variants with several Vt options and operating modes.
Designs needing ECC and redundancy
ECC bits plus redundancy through flexible addressing, with BIST and repair if you want it.
Find your node, then the part number
Millions of wafers and thousands of designs already carry Silvaco’s compiled memory.
Start with your foundry and node. If a compiler exists there today, it has a part number.
SRAM compilers by foundry and node
Size is the range of bits each compiler generates. Process not in the table? Ask an IP specialist about a port.
22–130 nm
part-numbered compilers at TSMC, GlobalFoundries and UMC
12 foundries and IDMs
where Silvaco memory compilers are deployed
0.28×
Standby leakage in Retention + Nap
25+ years
of compiled memory design
Liberty · LEF · GDSII
delivered with every characterized, DRC/LVS-clean instance
Catalog · PDF
Summer 2026
Silvaco IP catalog
Every SRAM compiler by foundry, node and part number, with retention, size, mux and supply for each.
Product brief · PDF
Summer 2026
Low Power Foundation IP
Low-power standard cells and SRAM power management on one sheet.
Webinar
Summer 2026
How to Design Ultra-low Power Embedded Memories with Silvaco Memory Compilers
Low-power techniques for embedded memory, built with Silvaco's memory compilers.
Webinar
Summer 2026
Achieving Extreme Low Power IoT Designs with Silvaco’s 55LPx Foundation IP Solution
Low-power foundation IP on GlobalFoundries 55LPx, the process behind compiler 61263.
News
Summer 2026
Silvaco acquires the memory compiler technology of Dolphin Design
The ultra-low-power, high-density compilers Silvaco acquired had served SoC designers for more than 25 years.
Ask about your node
Tell an IP specialist your foundry, node and the SRAM you need: capacity, ports and
power modes. You’ll learn whether there’s a compiler on it now, what porting one
would take, and how licensing works.
SRAM compiler questions
What is an SRAM compiler?
An SRAM compiler generates embedded SRAM instances to the capacity, mux and word width a design specifies, so nobody lays out each memory by hand. Silvaco's compilers deliver fully characterized, DRC/LVS-clean single- and dual-port instances for a named foundry process, with the power modes that process supports.
What is the difference between single and dual port SRAM?
A single-port SRAM handles one read or one write per cycle. A dual-port SRAM has two independent ports, so two accesses can land in the same cycle, and it takes more area to do it. Silvaco's catalog lists seven single-port and five dual-port compilers, all five dual-port on TSMC processes.
Which nodes and processes are supported?
Part-numbered compilers cover 22, 40, 55, 90, 110 and 130 nm: GlobalFoundries 22FDX+ and 55LPx, UMC 110 nm eFlash, and TSMC from 40 to 130 nm on low-power, eFlash, high-voltage and BCD processes. Silvaco's wider node list adds 180, 152, 85, 65 and 28 nm. And if yours isn't there, a port is worth asking about.
What are Nap and Retention modes?
Both are low-power states for an idle SRAM. Nap switches off the periphery and turns on source biasing, waking in one clock cycle at 0.69× Standby leakage, while Retention drops the core to the lowest data-holding voltage for 0.54×. Combine the two and leakage falls to 0.28×, on nodes from 55 nm down.
Is BIST and repair supported?
Yes, as an option. Built-in self test and repair (BIST/R) raises reliability and yield, and it works alongside ECC bits and the redundancy that configurable word size and addresses give you. The compilers are also checked for variation tolerance, local as well as global.
What does the compiler deliver?
Each compiled instance is fully characterized and DRC/LVS-clean, with the Liberty models, LEF abstract and GDSII layout your flow expects. Supply can be single or split between periphery and core, and a write mask is there when the design calls for one.
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Low Power Foundation IP
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