MIPI D-PHY
MIPI D-PHY IP: CSI-2 and DSI physical layer
Silicon-proven D-PHY transmitters, receivers and Universal PHYs for your camera and display links, from the Mixel team that took D-PHY to real silicon first.
What D-PHY is, and when you need it
Three questions settle whether D-PHY is the right PHY for your link.
What MIPI D-PHY is
It’s the physical layer under MIPI’s camera and display interfaces. Silvaco’s MIPI D-PHY IP follows the v3.5 specification and still works with earlier versions. You pick one to four data lanes, at up to 6.5 Gbps each, in TX, RX, TX+, RX+ or Universal form.
D-PHY or C-PHY
D-PHY sends data over lanes beside a separate clock. C-PHY folds the clock into three-wire trios and reaches 8.0 Gsps per trio. If your first constraint is the process, start with D-PHY, because it’s on far more of them. And if the design needs both, the C-PHY/D-PHY combo PHY switches between the two.
CSI-2 or DSI
CSI-2 is the camera side: sensor data coming into the SoC. DSI and DSI-2 are the display side, with pixels going out to the panel. Each transmitter and receiver is committed to one, and its part name tells you which. Universal PHYs aren’t. They take either role, master or slave, on either interface.
MIPI D-PHY IP by foundry and process
The first thing to check on any PHY: is it already in silicon on your process?
| Foundry | Product Name | Features | Part Number | Grade |
|---|---|---|---|---|
| TSMC | D-PHY DSI TX in TSMC N7 | Supports MIPI D-PHY, 4L, 4.5Gbps | ||
| GlobalFoundries | Supports MIPI D-PHY, 4L, 1.25Gbp | Supports MIPI D-PHY, 4L, 1.25Gbps | ||
| TSMC | D-PHY CSI-2 RX in TSMC 16FFC | Supports MIPI D-PHY, 4L, 1.25Gbps | ||
| GlobalFoundries | D-PHY CSI-2 TX in GF 22FDX | Supports MIPI D-PHY, 2L, 2.5Gbps | ||
| GlobalFoundries | D-PHY CSI-2 RX in GF 22FDX | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| GlobalFoundries | D-PHY CSI-2 RX in GF 22FDX | Supports MIPI D-PHY, 2L, 2.5Gbps | ||
| GlobalFoundries | D-PHY CSI-2 TX in GF 22FDX | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| GlobalFoundries | D-PHY DSI RX in GF 22FDX | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| GlobalFoundries | D-PHY DSI TX+ in GF 22FDX+ | Supports MIPI D-PHY, 2L, 2.5Gbps, full-speed internal loopback testability | ||
| GlobalFoundries | D-PHY CSI-2 RX in GF 22FDX+ | Supports MIPI D-PHY, 2L, 2.5Gbps | ||
| GlobalFoundries | D-PHY DSI-2 RX in GF 22FDX+ | Supports MIPI D-PHY, 2L, 2.5Gbps | ||
| TSMC | D-PHY CSI-2 TX in TSMC 22ULL | Supports MIPI D-PHY, 1L, 1.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY CSI-2 TX+ in TSMC 22ULL | Supports MIPI D-PHY, 4L, 2.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY Universal in TSMC 22ULL | Supports MIPI D-PHY, 4L, 2.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY Universal in TSMC 22ULP | Supports MIPI D-PHY, 4L, 2.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY Universal in TSMC 22ULP | Supports MIPI D-PHY, 2L, 2.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY Universal in TSMC 22ULP | Supports MIPI D-PHY, 2L, 2.5Gbps, full-speed internal loopback testability | ||
| UMC | D-PHY DSI RX in UMC 22ULP/22ULL | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| Samsung | D-PHY DSI TX+ in Samsung 28FDSOI | Supports MIPI D-PHY, 4L, 1.5Gbps, full-speed internal loopback testability | ||
| Samsung | D-PHY CSI-2 RX in Samsung 28FDSOI | Supports MIPI D-PHY, 2L, 1.5Gbps | ||
| TSMC | D-PHY CSI-2 TX+ in TSMC 28HPC+ | Supports MIPI D-PHY, 4L, 2.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY Universal in TSMC 28HPC+ | Supports MIPI D-PHY, 4L, 2.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY CSI-2 RX+ in TSMC 28HPC+ | Supports MIPI D-PHY, 2L, 1.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY DSI TX in TSMC 28HPC+ | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| TSMC | D-PHY CSI-2 RX in TSMC 28HPC+ | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| TSMC | D-PHY CSI-2 TX in TSMC 28HPC+ | Supports MIPI D-PHY, 2L, 2.5Gbps | ||
| TSMC | D-PHY Universal in TSMC 28HPC+ | Supports MIPI D-PHY, 4L, 2.5Gbps, full-speed internal loopback testability | ||
| SMIC | D-PHY CSI-2 TX+ in SMIC 28HPC+ | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| TSMC | D-PHY Universal in TSMC 40LP | Supports MIPI D-PHY, 1L, 1.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY CSI-2 TX in TSMC 40LP | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| TSMC | D-PHY CSI-2 TX+ in TSMC 40ULP | Supports MIPI D-PHY, 1L, 1.5Gbps, full-speed internal loopback testability | ||
| TSMC | D-PHY CSI-2 TX+ in TSMC 40ULP | Supports MIPI D-PHY, 4L, 1.5Gbps, full-speed internal loopback testability | ||
| SMIC | D-PHY CSI-2 TX+ in SMIC 28HPC+ | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| TSMC | D-PHY DSI TX in TSMC 55ULP | Supports MIPI D-PHY, 2L, 1.0Gbps | ||
| TSMC | D-PHY Universal in TSMC 65GP | Supports MIPI D-PHY, 4L, 2.5Gbps, full-speed internal loopback testability | ||
| Tower | D-PHY CSI-2 TX in Tower 65ISC | Supports MIPI D-PHY, 4L, 1.2Gbps | ||
| Tower | D-PHY CSI-2 TX in Tower 65ISC | Supports MIPI D-PHY, 2L, 1.2Gbps | ||
| TSMC | D-PHY CSI-2 TX in TSMC 65LP | Supports MIPI D-PHY, 2L, 2.5Gbs | ||
| TSMC | D-PHY CSI-2 TX in TSMC 65LP | Supports MIPI D-PHY, 4L, 1.5Gbs | ||
| TSMC | D-PHY CSI-2 TX in TSMC 90LP | Supports MIPI D-PHY, 4L, 2.5Gbps | ||
| TSMC | D-PHY CSI-2 TX+ in TSMC 90LP (90N65CIS) | Supports MIPI D-PHY, 4L, 2.5Gbps |
1L, 2L and 4L mean one, two and four data lanes, and every rate is per lane. A plus, as in TX+ or RX+, adds full-speed internal loopback testability. Process not listed? Talk to an IP specialist.
Where D-PHY sits in your system
Camera in, display out: most SoCs need at least one of each.
Camera interfaces using CSI-2
Image sensor into the SoC over CSI-2, on one, two or four lanes.
Display interfaces using DSI
SoC out to the panel over DSI, at up to 4.5 Gbps per lane on TSMC N7.
Automotive camera and display links
Multi-camera ADAS, surround-view and in-cabin screens, and radar too: indie runs ASIL-B D-PHY CSI-2 IP in its radar processors.
Mobile and wearable devices
Battery-powered phones and wearables, where D-PHY’s low-power modes decide how long a charge lasts.
Silicon you can check
Ask any IP vendor for two names: the process it ran on, and the customer who shipped it.
7 to 90 nm
D-PHY processes from TSMC N7 to TSMC 90LP
1 to 4 lanes
D-PHY v3.5, at up to 6.5 Gbps per lane
35% · 50%
less area and less leakage power with D-PHY RX+ than a full Universal PHY, with full-speed production test kept
12 nodes, 9 foundries
where Mixel PHY IP is silicon-proven across all its standards, 180 nm to 5 nm
ASIL-B
D-PHY CSI-2 TX and RX for automotive, designed to support AEC-Q100 Grade 1
Customer · MIPI D-PHY
November 2025
indie
indie’s automotive radar processors and MMICs run Mixel’s ASIL-B D-PHY CSI-2 transmitter and receiver. The IP came with certified functional safety deliverables and a safety manual. Mixel then characterized it inside indie’s design against the MIPI D-PHY Conformance Test Suite.
“We needed a MIPI IP provider that could support our strict automotive requirements to further our radar portfolio and enable efficient and scalable ADAS architecture solutions. Through our long-standing partnership with Mixel and their extensive automotive experience, we had full confidence in Mixel’s capabilities and reliability. We are looking forward to our continued collaboration.”
Peter Gulden, EVP Radar Systems and Software, indie
Catalog · PDF
Summer 2026
PRO IP product selection guide
Every D-PHY part number, graded commercial, industrial or automotive, beside the C-PHY, combo and LVDS parts. Each one ships with Liberty, LEF and GDSII views.
Press release
March 2026
Mixel MIPI PHY IP now available as PRO IP
What D-PHY v3.5 supports, all five implementations, and where RX+ gets its 35% area saving.
Is D-PHY on your node yet?
Give an IP specialist your foundry and node, and you’ll get a straight answer on licensing and availability for MIPI D-PHY, including processes not listed yet. You’ll be talking to the Mixel engineers who designed the PHY, and they stay with you through integration.
Questions about MIPI D-PHY IP
What is MIPI D-PHY?
MIPI D-PHY is the physical layer that carries MIPI’s camera interface, CSI-2, and its display interfaces, DSI and DSI-2, between chips. Silvaco’s MIPI D-PHY IP is built to the v3.5 specification and is backwards compatible. It supports one to four data lanes and up to 6.5 Gbps on each. You can license TX, RX, TX+, RX+ or Universal implementations.
What is the difference between CSI-2 and DSI?
CSI-2 is the camera serial interface: it moves image data from a sensor into the processor. DSI, and the newer DSI-2, is the display serial interface, which moves pixels from the processor to a panel. Any single D-PHY transmitter or receiver supports one of the two. A Universal D-PHY can be configured as master or slave for either.
When should I use D-PHY rather than C-PHY?
Choose D-PHY when you need the widest choice of foundry processes, or a lane-based link with its own clock. C-PHY encodes data across one to three trios, at up to 8.0 Gsps per trio, and Silvaco offers it on three parts against a far longer D-PHY list. If a design needs both, a combo PHY supports either mode.
Which foundries and nodes are available?
Silvaco’s D-PHY IP is listed on TSMC (N7, 16FFC, 22ULP, 22ULL, 28HPC+, 40LP, 40ULP, 55ULP, 65GP, 65LP, 90LP), GlobalFoundries (22FDX, 22FDX+), Samsung (28FDSOI), Tower (65ISC) and UMC (22ULP/22ULL). If yours isn’t listed, ask anyway. Across all its standards, Mixel has PHY IP in silicon at nine foundries and twelve nodes.
What data rates are supported?
Current D-PHY parts run from 1.0 to 4.5 Gbps per lane, and most run at 2.5 Gbps. The fastest is the DSI transmitter on TSMC N7, at 4.5 Gbps on four lanes. The D-PHY v3.5 design reaches 6.5 Gbps per lane, a rate Silvaco offers today in its C-PHY/D-PHY combo parts on TSMC 16FFC.
What does the plus suffix mean?
The plus marks TX+ and RX+ parts, which add full-speed internal loopback testability. RX+ is Mixel’s patented receiver topology: you can run full-speed production tests on it without building in a full D-PHY Universal PHY. Silvaco puts the saving at 35% in area and 50% in leakage power.
Related D-PHY and MIPI IP
MIPI
D-PHY, C-PHY and M-PHY side by side, to see which physical layer fits your link.
MIPI C-PHY
Three-wire trios instead of lanes, on TSMC 22ULL and 40ULP.
C-PHY/D-PHY Combo
One PHY that runs as C-PHY or D-PHY, on TSMC and ST processes.
D-PHY TX+
The transmitter with full-speed internal loopback built in.
D-PHY RX+
Full-speed production testing in 35% less area than a Universal PHY.