Casey Molver

Introduction It is widely believed that the scaling of standard Flash devices will face in a near future several limitations, due to the high voltage requirement of the program/erase and

Abstract In this paper we present an original semi-analytical model for the subthreshold electrical behavior of complex 3D structures as the SOI FinFLASH devices. This physically-based model, which does not

Q. Is it possible to calculate the resistance components of a MOSFET (i.e. channel resistance, epi resistance, substrate resistance etc.) as a function of gate bias?

Introduction The physical verification is becoming the most complex phase raised by the Deep SubMicron (DSM) technology. More than 50% of the design time is dedicated to the verification. With

Introduction The trend toward smaller MOSFET devices with thinner gate oxide and greater doping is resulting in the increased importance of quantum mechanical effects, which are observed as shifts in

Introduction Erasable programmable read-only memory (EPROM) devices include amongst others, floating gate technology and SONOS (Polysilicon-Oxide-Nitride-Silicon) technology. Floating gate technology involves charge being stored in the polysilicon floating gate as

How to obtain a stable grid and smooth doping profile in non-planar a-Si TFT using Athena/Elite?

Abstract Improvement in temperature characteristics of GaN LEDs is important for realizing reliable devices operating at high temperatures. In this article, the thermal characteristics of GaN LEDs have been analyzed

Introduction By default STELLAR calculates the capacitances between interconnect lines and the whole substrate. In certain conditions it may lead to some inaccuracies. For example STELLAR may calculate the capacitance

1. Introduction Amorphous oxide semiconductor materials have attracted much attention as key components of TFTs for flexible electronics [1]. The advantages of such materials include flexibility and transparency which are

Polarization-induced charges at the AlGaN/GaN interface of heterojunction field-effect transistors (HFETs) create a high density, two-dimensional electron gas (2DEG) in the channel. One approach to simulating the 2DEG is to

Interconnect parasitic effects play a very important role in modern integrated circuit design, especially for digital circuit. This article presents how a cell level BiCMOS nand gate is extracted with