Casey Molver

Introduction In modern power devices, the total power loss comprises both a conductive power loss component and a capacitive loss component. As the cell pitch decreases, the conductive loss will

Introduction The Monte Carlo Implantation Module of ATHENA has proved to be a very accurate tool for simulation of various implantation processes. In this paper we demonstrate that the module

Is there a way to turn-off all of the generated layers so that the layout modifications can be done without them cluttering things?

Expert features a powerful Netlist Driven Layout (NDL) function to assist the user in creating a layout. It increases the productivity of layout design by automating cell generation and providing

Expert Parametric Wire (Pwire) is a complex group of objects containing, a single wire named master wire, any number of subparts such as enclosure wires, offset wires and sets of

I am currently using ATLAS/ Blaze to model the electrical properties of an LED device that I am investigating. Is it possible to examine the reverse ray trace from my

Organic light emitting diodes (OLEDs) are attracting great interest in the display technology industry due to their promising low cost large area manufacturing and relative ease of fabrication using low

The persistent semiconductor technology trend of shrinking down device size requires development of veryaggressive technological setups consisting in high dose/low energy implants, followed by rapid thermal anneals (RTA).

The wiring tool in Expert automatically creates the shortest wire connecting two points specified by the user. The created wire goes around any existing layout objects. It may lie in

Q. I have to send copies of my project layout to different members of my group, but they need to see only specific layers of the layout. How can I

Introduction The functionality Silvaco’s Layou Editor, Expert, has recently been expanded with the new feature called Layout Versus Layout comparison (LVL). LVL is available as a separate window called by

In deep submicron technology, conduction layers have widths much smaller than their thicknesses (see Figure 1). This makes edge parasitic capacitance effects more dominant than plate capacitance. In a multi-body